KR960039184A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960039184A
KR960039184A KR1019950008055A KR19950008055A KR960039184A KR 960039184 A KR960039184 A KR 960039184A KR 1019950008055 A KR1019950008055 A KR 1019950008055A KR 19950008055 A KR19950008055 A KR 19950008055A KR 960039184 A KR960039184 A KR 960039184A
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KR
South Korea
Prior art keywords
semiconductor device
manufacturing
polycrystalline silicon
etching
refractory metal
Prior art date
Application number
KR1019950008055A
Other languages
Korean (ko)
Other versions
KR100327420B1 (en
Inventor
이계남
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950008055A priority Critical patent/KR100327420B1/en
Publication of KR960039184A publication Critical patent/KR960039184A/en
Application granted granted Critical
Publication of KR100327420B1 publication Critical patent/KR100327420B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 반도체장치 제조시 플라즈마 식각에 기인한 다결정실리콘 및 내화성 금속실리사이드의 측벽중합체를 제거하기 위한 것이다. 본 발명은 반도체장치의 도전성 형성을 위해 다결정실리콘 및 내화성 금속실리사이드를 CL2계통의 가스를 포함한 혼합가스를 사용한 플라즈마 식각에 의해 식각하는 반도체장치의 제조방법에 있어서, 상기 플라즈마 식각에 의해 상기 다결정실리콘 및 내화성 금속실리사이드를 식각한 후에 CL-를 포함하는 화합물을 식각원으로하는 혼합액을 사용하여 습식처리를 행하는 것을 특징으로 하는 반도체장치 제조방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and to remove sidewall polymers of polycrystalline silicon and refractory metal silicide due to plasma etching during semiconductor device manufacturing. The present invention provides a method of manufacturing a semiconductor device in which polycrystalline silicon and refractory metal silicide are etched by plasma etching using a mixed gas containing a CL 2 -based gas to form a conductive structure of the semiconductor device, wherein the polycrystalline silicon is formed by the plasma etching. And a wet treatment using a mixed solution containing a CL − -containing compound as an etching source after etching the refractory metal silicide.

Description

반도체장치 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 플라즈마 식각에 기인한 다결정실리콘 및 내화성 금속실리사이드의 측벽중합체를 도시한 도면, 제4도는 본 발명에 의해 측벽중합체를 제거한 경우를 나타낸 도면.1 is a view showing sidewall polymers of polycrystalline silicon and refractory metal silicides due to plasma etching, and FIG. 4 is a view showing a case where sidewall polymers are removed according to the present invention.

Claims (3)

반도체장치의 도전성 형성을 위해 다결정실리콘 및 내화성 금속실리사이드를 CL2계통의 가스를 포함한 혼합가스를 사용한 플라즈마 식각에 의해 식각하는 반도체장치의 제조방법에 있어서, 상기 플라즈마 식각에 의해 상기 다결정실리콘 및 내화성 금속실리사이드를 식각한후에 CL-를 포함하는 화합물을 식각원으로 하는 혼합액을 사용하여 습식처리를 행하는 것을 특징으로 하는 반도체장치 제조방법.A method of manufacturing a semiconductor device in which polycrystalline silicon and refractory metal silicide are etched by plasma etching using a mixed gas containing a CL 2 -based gas to form a semiconductor device, wherein the polycrystalline silicon and refractory metal are etched by the plasma etching. A method of manufacturing a semiconductor device, characterized in that the wet treatment is performed using a mixed solution containing CL − as an etching source after etching the silicide. 제1항에 있어서, 상기 CI-를 포함한 화합물로 HCL, NaCL, POCL3, C2H2CI3를 사용하는 것을 특징으로 하는 반도체장치 제조방법.The method of claim 1, wherein HCl, NaCL, POCL 3 , and C 2 H 2 CI 3 are used as the compound containing CI − . 제1항에 있어서, 상기 혼합액으로 상기 C-기를 포함한 화합물에 H2O2및 H2O의 희석액이 혼합된 것을 사용하는 것을 특징으로 하는 반도체장치 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein a diluent of H 2 O 2 and H 2 O is mixed with the compound including the C − group as the mixed solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950008055A 1995-04-07 1995-04-07 Method for fabricating semiconductor device KR100327420B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008055A KR100327420B1 (en) 1995-04-07 1995-04-07 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008055A KR100327420B1 (en) 1995-04-07 1995-04-07 Method for fabricating semiconductor device

Publications (2)

Publication Number Publication Date
KR960039184A true KR960039184A (en) 1996-11-21
KR100327420B1 KR100327420B1 (en) 2002-07-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950008055A KR100327420B1 (en) 1995-04-07 1995-04-07 Method for fabricating semiconductor device

Country Status (1)

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KR (1) KR100327420B1 (en)

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Publication number Publication date
KR100327420B1 (en) 2002-07-22

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