KR960019530A - Align target formation method of semiconductor device - Google Patents

Align target formation method of semiconductor device Download PDF

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Publication number
KR960019530A
KR960019530A KR1019940028516A KR19940028516A KR960019530A KR 960019530 A KR960019530 A KR 960019530A KR 1019940028516 A KR1019940028516 A KR 1019940028516A KR 19940028516 A KR19940028516 A KR 19940028516A KR 960019530 A KR960019530 A KR 960019530A
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KR
South Korea
Prior art keywords
oxide film
etching
semiconductor device
forming
alignment
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Application number
KR1019940028516A
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Korean (ko)
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KR0140636B1 (en
Inventor
이상중
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019940028516A priority Critical patent/KR0140636B1/en
Publication of KR960019530A publication Critical patent/KR960019530A/en
Application granted granted Critical
Publication of KR0140636B1 publication Critical patent/KR0140636B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체장치의 얼라인타겟 형성방법에 관한 것으로, 자동정렬시의 정확도를 향상시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an alignment target of a semiconductor device, and to improve accuracy in automatic alignment.

본 발명은 실리콘기판상에 산화막을 형성하는 공정과, 상기 산화막의 소정부분을 식각된 부분의 경사각이 직각에 가깝도록 식각하는 공정, 상기 산화막의 식각에 의해 노출된 기판부분에 불순물을 도핑하는 공정, 및 상기 산화막을 제거하는 공정으로 이루어지는 반도체장치의 얼라인타겟 형성방법을 제공함으로써 실리콘 얼라인타겟의 경사각을 직각에 가깝게 형성하여 얼라인공정시의 정확도를 향상시킨다.The present invention provides a process for forming an oxide film on a silicon substrate, etching a predetermined portion of the oxide film so that the inclination angle of the etched portion is close to a right angle, and doping an impurity in a portion of the substrate exposed by the etching of the oxide film. By providing a method for forming an alignment target of a semiconductor device comprising the step of removing the oxide film, the inclination angle of the silicon alignment target is formed close to the right angle to improve the accuracy during the alignment process.

Description

반도체장치의 얼라인타겟(Align target) 형성방법Align target formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 반도체장치의 얼라인타겟 형성방법을 도시한 공정순서도.2 is a process flowchart showing an alignment target forming method of a semiconductor device of the present invention.

Claims (3)

실리콘기판상에 산화막을 형성하는 공정과, 상기 산화막의 소정부분을 시각된 부분의 경사각이 직각에 가깝도록 식각하는 공정, 상기 산화막의 식각에 의해 노출된 기판부분에 불순물을 도핑하는 공정, 및 상기 산화막을 제거하는 공정으로 이루어지는 것을 특징으로 하는 반도체장치의 얼라인타겟 형성방법.Forming an oxide film on a silicon substrate, etching a predetermined portion of the oxide film such that the inclination angle of the visible portion is close to a right angle, doping an impurity in a portion of the substrate exposed by etching the oxide film, and An alignment target forming method of a semiconductor device, comprising the step of removing an oxide film. 제1항에 있어서, 상기 산화막의 식각은 식각시간을 산화막두께만큼을 완전히 식각해낼 수 있는 시간보다 적어도 10%이상 증가시킨 습식식각을 이용하여 행하는 것을 특징으로 하는 반도체장치의 얼라인타겟 형성방법.The method of claim 1, wherein the etching of the oxide film is performed by using a wet etching method in which the etching time is increased by at least 10% more than the time capable of completely etching the oxide film thickness. 제1항에 있어서, 상기 산화막의 식각은 건식식각에 의해 행하는 것을 특징으로 하는 반도체장치의 얼라인타겟 형성방법.The method of claim 1, wherein the etching of the oxide film is performed by dry etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028516A 1994-11-01 1994-11-01 Forming method of aligntarget in the semiconkuctor device KR0140636B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940028516A KR0140636B1 (en) 1994-11-01 1994-11-01 Forming method of aligntarget in the semiconkuctor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940028516A KR0140636B1 (en) 1994-11-01 1994-11-01 Forming method of aligntarget in the semiconkuctor device

Publications (2)

Publication Number Publication Date
KR960019530A true KR960019530A (en) 1996-06-17
KR0140636B1 KR0140636B1 (en) 1998-07-15

Family

ID=19396827

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940028516A KR0140636B1 (en) 1994-11-01 1994-11-01 Forming method of aligntarget in the semiconkuctor device

Country Status (1)

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KR (1) KR0140636B1 (en)

Also Published As

Publication number Publication date
KR0140636B1 (en) 1998-07-15

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