JPS558032A - Semi-conductor device manufacturing method - Google Patents

Semi-conductor device manufacturing method

Info

Publication number
JPS558032A
JPS558032A JP8011478A JP8011478A JPS558032A JP S558032 A JPS558032 A JP S558032A JP 8011478 A JP8011478 A JP 8011478A JP 8011478 A JP8011478 A JP 8011478A JP S558032 A JPS558032 A JP S558032A
Authority
JP
Japan
Prior art keywords
insulation film
contact region
opening
semi
pinhole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8011478A
Other languages
Japanese (ja)
Inventor
Michihiro Oota
Kunio Kokubu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8011478A priority Critical patent/JPS558032A/en
Publication of JPS558032A publication Critical patent/JPS558032A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To improve reliability of a semi-conductor device by reducing size of a contact region so that the device can be made smaller and unfaborable or undesirable shortcircuit due to pinhole on insulation film can be remarkably decreased.
CONSTITUTION: An opening 4 is bored on an insulation film 2 by a resist mask 3 on a P layer 2 formed on an N-type Si base plate 1. The mask 3 is removed, and an insulation film 5, which is sufficiently thinner than the insulation film 2, is provided. A resist mask 6, having an opening 7 larger than the opening 4, is provided and insulation films 5 and 2 are etched. At this time, the etching process is to be stopped when the thin film 5 of the contact region 4 is completely removed and the thick film 2 is slightly etched. And then, a metallic wiring 8 is formed. As the contact region between the wiring and the base plate is determined by mutually independent insulation film formation of more than 2 times and photographic etching, shortcircuit due to pinhole can be almost eliminated. As it is also possible to provide the contact region with a window by only one processing with high accuracy, simplification of manufacturing process can be achieved.
COPYRIGHT: (C)1980,JPO&Japio
JP8011478A 1978-06-30 1978-06-30 Semi-conductor device manufacturing method Pending JPS558032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8011478A JPS558032A (en) 1978-06-30 1978-06-30 Semi-conductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8011478A JPS558032A (en) 1978-06-30 1978-06-30 Semi-conductor device manufacturing method

Publications (1)

Publication Number Publication Date
JPS558032A true JPS558032A (en) 1980-01-21

Family

ID=13709150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8011478A Pending JPS558032A (en) 1978-06-30 1978-06-30 Semi-conductor device manufacturing method

Country Status (1)

Country Link
JP (1) JPS558032A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110229A (en) * 1980-02-06 1981-09-01 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110229A (en) * 1980-02-06 1981-09-01 Nec Corp Manufacture of semiconductor device

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