KR960015275A - 입/출력 채널 제어기, 멀티프로세싱 시스템 및 데이타 프로세싱 방법 - Google Patents

입/출력 채널 제어기, 멀티프로세싱 시스템 및 데이타 프로세싱 방법 Download PDF

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Publication number
KR960015275A
KR960015275A KR1019950033597A KR19950033597A KR960015275A KR 960015275 A KR960015275 A KR 960015275A KR 1019950033597 A KR1019950033597 A KR 1019950033597A KR 19950033597 A KR19950033597 A KR 19950033597A KR 960015275 A KR960015275 A KR 960015275A
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South Korea
Prior art keywords
operations
input
data processing
completion
output channel
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KR1019950033597A
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English (en)
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KR0163231B1 (ko
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Small-Scale Networks (AREA)
KR1019950033597A 1994-10-03 1995-09-30 입/출력 채널 제어기, 멀티 프로세싱 시스템 및 데이타 프로세싱 방법 KR0163231B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US8/316,977 1994-10-03
US08/316,977 US5613153A (en) 1994-10-03 1994-10-03 Coherency and synchronization mechanisms for I/O channel controllers in a data processing system

Publications (2)

Publication Number Publication Date
KR960015275A true KR960015275A (ko) 1996-05-22
KR0163231B1 KR0163231B1 (ko) 1999-01-15

Family

ID=23231561

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950033597A KR0163231B1 (ko) 1994-10-03 1995-09-30 입/출력 채널 제어기, 멀티 프로세싱 시스템 및 데이타 프로세싱 방법

Country Status (8)

Country Link
US (1) US5613153A (ko)
EP (1) EP0731944B1 (ko)
JP (1) JP3280207B2 (ko)
KR (1) KR0163231B1 (ko)
AT (1) ATE210855T1 (ko)
DE (1) DE69524564T2 (ko)
ES (1) ES2164781T3 (ko)
WO (1) WO1996011430A2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
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KR100353656B1 (ko) * 1999-03-31 2002-09-19 인터내셔널 비지네스 머신즈 코포레이션 Ｄｍａ 및 ｌ1/ｌ2 캐시 성능을 향상시키기 위한 방법, 장치 및 컴퓨터 프로그램 기록 매체

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KR100353656B1 (ko) * 1999-03-31 2002-09-19 인터내셔널 비지네스 머신즈 코포레이션 Ｄｍａ 및 ｌ1/ｌ2 캐시 성능을 향상시키기 위한 방법, 장치 및 컴퓨터 프로그램 기록 매체

Also Published As

Publication number Publication date
US5613153A (en) 1997-03-18
DE69524564D1 (de) 2002-01-24
WO1996011430A2 (en) 1996-04-18
ES2164781T3 (es) 2002-03-01
JPH08115260A (ja) 1996-05-07
DE69524564T2 (de) 2002-08-22
EP0731944A1 (en) 1996-09-18
JP3280207B2 (ja) 2002-04-30
EP0731944B1 (en) 2001-12-12
WO1996011430A3 (en) 1996-07-18
KR0163231B1 (ko) 1999-01-15
ATE210855T1 (de) 2001-12-15

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