KR960008518B1 - Manufacturing method and apparatus of semiconductor device - Google Patents

Manufacturing method and apparatus of semiconductor device Download PDF

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Publication number
KR960008518B1
KR960008518B1 KR92017555A KR920017555A KR960008518B1 KR 960008518 B1 KR960008518 B1 KR 960008518B1 KR 92017555 A KR92017555 A KR 92017555A KR 920017555 A KR920017555 A KR 920017555A KR 960008518 B1 KR960008518 B1 KR 960008518B1
Authority
KR
South Korea
Prior art keywords
forming
spacer
semiconductor substrate
trench
polysilicon
Prior art date
Application number
KR92017555A
Other languages
English (en)
Other versions
KR930009016A (ko
Inventor
Tae-Seo Park
Yun-Ki Kim
Dong-Chol Park
Sung-Tae Ahn
Byung-Ryul Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR92017555A priority Critical patent/KR960008518B1/ko
Publication of KR930009016A publication Critical patent/KR930009016A/ko
Priority to US08/127,155 priority patent/US5360753A/en
Application granted granted Critical
Publication of KR960008518B1 publication Critical patent/KR960008518B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
KR92017555A 1991-10-02 1992-09-25 Manufacturing method and apparatus of semiconductor device KR960008518B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR92017555A KR960008518B1 (en) 1991-10-02 1992-09-25 Manufacturing method and apparatus of semiconductor device
US08/127,155 US5360753A (en) 1992-09-25 1993-09-27 Manufacturing method for a semiconductor isolation region

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR91-17324 1991-10-02
KR910017324 1991-10-02
KR92017555A KR960008518B1 (en) 1991-10-02 1992-09-25 Manufacturing method and apparatus of semiconductor device

Publications (2)

Publication Number Publication Date
KR930009016A KR930009016A (ko) 1993-05-22
KR960008518B1 true KR960008518B1 (en) 1996-06-26

Family

ID=19340127

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92017555A KR960008518B1 (en) 1991-10-02 1992-09-25 Manufacturing method and apparatus of semiconductor device

Country Status (2)

Country Link
US (1) US5360753A (ko)
KR (1) KR960008518B1 (ko)

Families Citing this family (38)

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US5851887A (en) * 1994-09-07 1998-12-22 Cypress Semiconductor Corporation Deep sub-micron polysilicon gap formation
US5598021A (en) * 1995-01-18 1997-01-28 Lsi Logic Corporation MOS structure with hot carrier reduction
US5455194A (en) * 1995-03-06 1995-10-03 Motorola Inc. Encapsulation method for localized oxidation of silicon with trench isolation
JP3360970B2 (ja) * 1995-05-22 2003-01-07 株式会社東芝 半導体装置の製造方法
KR0151049B1 (ko) * 1995-05-29 1998-12-01 김광호 반도체장치의 소자분리방법
US5629230A (en) * 1995-08-01 1997-05-13 Micron Technology, Inc. Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion
US6967369B1 (en) 1995-09-20 2005-11-22 Micron Technology, Inc. Semiconductor memory circuitry
US7705383B2 (en) * 1995-09-20 2010-04-27 Micron Technology, Inc. Integrated circuitry for semiconductor memory
KR100190010B1 (ko) * 1995-12-30 1999-06-01 윤종용 반도체 소자의 소자분리막 형성방법
US5904543A (en) * 1996-03-28 1999-05-18 Advanced Micro Devices, Inc Method for formation of offset trench isolation by the use of disposable spacer and trench oxidation
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US5929476A (en) 1996-06-21 1999-07-27 Prall; Kirk Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors
KR100190048B1 (ko) * 1996-06-25 1999-06-01 윤종용 반도체 소자의 소자 분리 방법
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates
KR100418299B1 (ko) * 1996-10-09 2004-05-14 주식회사 하이닉스반도체 반도체소자의필드산화막형성방법
JPH10199875A (ja) * 1997-01-10 1998-07-31 Nec Corp 半導体装置の製造方法
TW388100B (en) * 1997-02-18 2000-04-21 Hitachi Ulsi Eng Corp Semiconductor deivce and process for producing the same
US6090685A (en) * 1997-08-22 2000-07-18 Micron Technology Inc. Method of forming a LOCOS trench isolation structure
KR100253078B1 (ko) 1997-12-23 2000-04-15 윤종용 반도체 장치의 트렌치 격리 형성 방법
US5945724A (en) * 1998-04-09 1999-08-31 Micron Technology, Inc. Trench isolation region for semiconductor device
KR100286736B1 (ko) 1998-06-16 2001-04-16 윤종용 트렌치 격리 형성 방법
US6054364A (en) * 1998-09-08 2000-04-25 Advanced Micro Devices Chemical mechanical polishing etch stop for trench isolation
US6323105B1 (en) * 1998-11-09 2001-11-27 United Microelectronics Corp. Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure
TW396508B (en) * 1999-01-05 2000-07-01 Mosel Vitelic Inc A method for forming trench isolation
US6306726B1 (en) 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide
US6500744B2 (en) 1999-09-02 2002-12-31 Micron Technology, Inc. Methods of forming DRAM assemblies, transistor devices, and openings in substrates
US6187650B1 (en) * 1999-11-05 2001-02-13 Promos Tech., Inc. Method for improving global planarization uniformity of a silicon nitride layer used in the formation of trenches by using a sandwich stop layer
US6413836B1 (en) * 2000-09-20 2002-07-02 Vanguard International Semiconductor Corporation Method of making isolation trench
KR100418576B1 (ko) * 2001-06-30 2004-02-11 주식회사 하이닉스반도체 반도체 소자의 트렌치형 소자분리막 형성방법
US6583060B2 (en) * 2001-07-13 2003-06-24 Micron Technology, Inc. Dual depth trench isolation
US6667224B1 (en) * 2001-08-13 2003-12-23 Cypress Semiconductor Corp. Method to eliminate inverse narrow width effect in small geometry MOS transistors
KR100480625B1 (ko) * 2002-10-24 2005-03-31 삼성전자주식회사 트렌치 소자분리막 형성방법 및 그 소자분리막을 구비하는반도체 소자
US7019348B2 (en) * 2004-02-26 2006-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded semiconductor product with dual depth isolation regions
FR2879020B1 (fr) * 2004-12-08 2007-05-04 Commissariat Energie Atomique Procede d'isolation de motifs formes dans un film mince en materiau semi-conducteur oxydable
US20070281403A1 (en) * 2006-06-01 2007-12-06 Mon-Chin Tsai Method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing
KR102319200B1 (ko) * 2015-11-05 2021-10-28 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9865495B2 (en) * 2015-11-05 2018-01-09 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US20200135898A1 (en) * 2018-10-30 2020-04-30 International Business Machines Corporation Hard mask replenishment for etching processes

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60241231A (ja) * 1984-05-15 1985-11-30 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置の製法
US5004703A (en) * 1989-07-21 1991-04-02 Motorola Multiple trench semiconductor structure method
JP2641781B2 (ja) * 1990-02-23 1997-08-20 シャープ株式会社 半導体素子分離領域の形成方法

Also Published As

Publication number Publication date
US5360753A (en) 1994-11-01
KR930009016A (ko) 1993-05-22

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