KR960009112B1 - Method for producing dram of semiconductor device - Google Patents

Method for producing dram of semiconductor device Download PDF

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Publication number
KR960009112B1
KR960009112B1 KR92015639A KR920015639A KR960009112B1 KR 960009112 B1 KR960009112 B1 KR 960009112B1 KR 92015639 A KR92015639 A KR 92015639A KR 920015639 A KR920015639 A KR 920015639A KR 960009112 B1 KR960009112 B1 KR 960009112B1
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KR
South Korea
Prior art keywords
forming
insulator
whole surface
conductor
region
Prior art date
Application number
KR92015639A
Other languages
Korean (ko)
Other versions
KR940004826A (en
Inventor
Nam-Kyu Park
Original Assignee
Lg Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Semicon Co Ltd filed Critical Lg Semicon Co Ltd
Priority to KR92015639A priority Critical patent/KR960009112B1/en
Publication of KR940004826A publication Critical patent/KR940004826A/en
Application granted granted Critical
Publication of KR960009112B1 publication Critical patent/KR960009112B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The DRAM is prepared by defining active and field regions by growing the field oxide layer(2) on wafer(1), and forming gates by depositing a 1st crystal silicone(4) and patterning; forming N- region(20) by implanting ions, and depositing the 1st insulator(21) on the surface except the center of gate and then forming a conductor(22) on the whole surface; removing the 1st insulator(21) and conductor(22) of the capacitor contact region, and forming a side wall insulator(23) on both sides of the conductor(22) and then forming N+ region(24) by implanting ions; forming a 2nd insulator(25) on the surface except the capacitor contact region and patterning the capacitor on the whole surface; forming a 3rd insulator(29) on the whole surface, removing the 3rd insulator(29) of metal contact region and then forming bit line(31) on the whole surface.
KR92015639A 1992-08-29 1992-08-29 Method for producing dram of semiconductor device KR960009112B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92015639A KR960009112B1 (en) 1992-08-29 1992-08-29 Method for producing dram of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92015639A KR960009112B1 (en) 1992-08-29 1992-08-29 Method for producing dram of semiconductor device

Publications (2)

Publication Number Publication Date
KR940004826A KR940004826A (en) 1994-03-16
KR960009112B1 true KR960009112B1 (en) 1996-07-10

Family

ID=19338698

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92015639A KR960009112B1 (en) 1992-08-29 1992-08-29 Method for producing dram of semiconductor device

Country Status (1)

Country Link
KR (1) KR960009112B1 (en)

Also Published As

Publication number Publication date
KR940004826A (en) 1994-03-16

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