KR940004826A - DRAM manufacturing method of semiconductor device - Google Patents

DRAM manufacturing method of semiconductor device Download PDF

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Publication number
KR940004826A
KR940004826A KR1019920015639A KR920015639A KR940004826A KR 940004826 A KR940004826 A KR 940004826A KR 1019920015639 A KR1019920015639 A KR 1019920015639A KR 920015639 A KR920015639 A KR 920015639A KR 940004826 A KR940004826 A KR 940004826A
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South Korea
Prior art keywords
insulator
forming
conductor
entire surface
region
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KR1019920015639A
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Korean (ko)
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KR960009112B1 (en
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박남규
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 하이 스피드 동작에 적당하도록 한 반도체 장치의 디램 제조방법에 관한 것으로 종래에는 디램의 스피드 개선을 위해 게이트 길이를 줄여 채널을 짧게 할 경우 쇼트 채널이 발생하는 결점이 있었으나, 본 발명에서는 텅스텐으로 게이트를 캡슐 형태로 둘러싸서, 상호 연락 지연을 억제하므로써 디램의 하이스피드르 실현하여 상기 결점을 개선시킬수 있는 것이다.The present invention relates to a method for manufacturing a DRAM of a semiconductor device that is suitable for high speed operation. In the related art, a short channel is generated when the channel length is shortened by shortening the gate length to improve the speed of the DRAM. By enclosing the gate in the form of a capsule, it is possible to improve the defect by realizing high speed of the DRAM by suppressing the interconnection delay.

Description

반도체 장치의 디램 제조방법DRAM manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 디램 제조의 일실시예를 설명하기 위한 공정단면도.Figure 2 is a cross-sectional view for explaining an embodiment of the DRAM manufacturing of the present invention.

Claims (11)

도전형 기판 상부에 필드산화막(2)을 성장하여 활성영역과 필드영역을 정의하고, 표면에 게이트 산화막(3), 제1차 다결정 규소(4)를 중착 및 패터닝하여 게이트를 형성하는 단계와, 이온을 주입하여 N-영역(20)을 형성하고, 게이트의 가운데 부분을 제외한 표현에 제1절연체(21)를 증착한후 전표면에 도전체(22)를 형성하는 단계와, 캐패시터 콘택영역의 제1절연체(21)와 도전체(22)을 제거하고, 도전체(22)의 양측면에 측벽 절열체(23)을 형성한후 이온을 주입하여 N+영역(24)을 형성하는 단계와, 상기 캐패시터 콘택 영역을 제외한 표면에 제2절연체(25)을 형성하고, 전표면에 캐패시터를 패터닝하는 단계와, 전표면에 제3절연체(29)를 형성하고, 금속콘택 영역의 제3절연체(29)를 제거한 후 전표면에 비트라인(31)을 형성하는 단계를 차례로 실시하여 이루어짐을 특징으로 하는 반도체 장치의 디램 제조방법.Growing a field oxide film 2 on the conductive substrate to define an active region and a field region, and forming a gate by depositing and patterning the gate oxide film 3 and the first polycrystalline silicon 4 on the surface; Implanting ions to form an N-region 20, depositing a first insulator 21 on a representation excluding the center portion of the gate, and then forming a conductor 22 on the entire surface of the capacitor contact region. Removing the first insulator 21 and the conductor 22, forming sidewall insulators 23 on both sides of the conductor 22, and implanting ions to form the N + region 24; Forming a second insulator 25 on a surface excluding the capacitor contact region, patterning a capacitor on the entire surface, forming a third insulator 29 on the entire surface, and forming a third insulator 29 in the metal contact region. After removing the step of forming a bit line 31 on the entire surface in sequence DRAM manufacturing method of a semiconductor device to. 제1항에 있어서, 비트라인(31)전표면에 평탄화용 절연체(32), 도전체를 차례로 형성하고, 도전체를 패터닝하여 제2전극(33)을 형성하는 단계와, 전표면에 보호막(34)을 도포하는 단계를 차례로 실시하여 이루어짐을 특징으로 하는 반도체 장치의 디램 제조방법.2. The method of claim 1, wherein the planarization insulator 32 and the conductor are sequentially formed on the entire surface of the bit line 31, and the conductor is patterned to form the second electrode 33. 34) A method for manufacturing a DRAM of a semiconductor device, comprising the steps of applying the coating step by step. 제2항에 있어서, 제2전극(33)으로 알루미늄을 사용하는 반도체 장치의 디램 제조방법.The method of claim 2, wherein aluminum is used as the second electrode (33). 제2항에 있어서, 보호막(34)은 규소질화막으로 이루어짐을 특징으로 하는 반도체 장치의 디램 제조방법.3. The method of claim 2, wherein the protective film (34) is made of a silicon nitride film. 제2항에 있어서, 평탄화용 절연체(32)로 TEOS 또는 SOG를 사용함을 특징으로 하는 반도체 장치의 디램제조방법.3. The method of claim 2, wherein TEOS or SOG is used as the planarization insulator (32). 제1항에 있어서, 측벽절연체(23)를 전표면에 절연체를 형성한후 절연체를 반응성 이온 식각하여 형성함을 특징으로 하는 반도체 장치의 디램 제조방법.2. The method of claim 1, wherein the sidewall insulator is formed on the entire surface of the sidewall insulator, and then the insulator is formed by reactive ion etching. 제1항에 있어서, 비트라인(31)형성전에 금속 콘택위에 패드용 도전체를 증착하여 제1전극(30)을 형성함을 특징으로 하는 반도체 장치의 디램 제조방법.The method of claim 1, wherein a pad conductor is deposited on the metal contact before the bit line (31) is formed to form a first electrode (30). 제1항에 있어서, 도전체(22)로 텅스텐을 사용함을 특징으로 하는 반도체 장치의 디램 제조방법.The method of manufacturing a DRAM of a semiconductor device according to claim 1, wherein tungsten is used as the conductor. 제8항에 있어서, 텅스텐은 WF6와 SiH4를 325℃에서 SiH4/WF6가 1.6이상이 되는 플로우를 하여 형성됨을 특징으로 하는 반도체 장치의 디램 제조방법.The method of claim 8, wherein the tungsten is formed by flowing a WF 6 and SiH 4 at a temperature of 325 ° C., wherein SiH 4 / WF 6 is 1.6 or more. 제1항에 있어서, 캐패시터는 하측전극(26), 유전체막(27), 상측전극(28)을 차례로 형성하여 이루어짐을 특징으로 하는 반도체 장치의 디램 제조방법.The method of claim 1, wherein the capacitor is formed by sequentially forming the lower electrode (26), the dielectric film (27), and the upper electrode (28). 제10항에 있어서, 상,하측 전극(28, 26)은 불순물이 도프된 다결정 규소로 이루어짐을 특징으로 하는 반도체 장치의 디램 제조방법.The method of claim 10, wherein the upper and lower electrodes (28, 26) are made of polycrystalline silicon doped with impurities. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92015639A 1992-08-29 1992-08-29 Method for producing dram of semiconductor device KR960009112B1 (en)

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KR92015639A KR960009112B1 (en) 1992-08-29 1992-08-29 Method for producing dram of semiconductor device

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KR940004826A true KR940004826A (en) 1994-03-16
KR960009112B1 KR960009112B1 (en) 1996-07-10

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