KR960002917A - Liquid crystal display for improving aperture ratio and manufacturing method thereof - Google Patents

Liquid crystal display for improving aperture ratio and manufacturing method thereof Download PDF

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KR960002917A
KR960002917A KR1019940014187A KR19940014187A KR960002917A KR 960002917 A KR960002917 A KR 960002917A KR 1019940014187 A KR1019940014187 A KR 1019940014187A KR 19940014187 A KR19940014187 A KR 19940014187A KR 960002917 A KR960002917 A KR 960002917A
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South Korea
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film
electrode
patterning
depositing
transparent conductive
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KR1019940014187A
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Korean (ko)
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KR0124976B1 (en
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노부유키 야마무라
장인식
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김광호
삼성전자 주식회사
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Priority to US08/493,000 priority patent/US5663575A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Abstract

유리기판상에, 게이트 라인 및 커패시터의 제1 전극으로서 사다리 형태로 투명 도전막을 증착, 패턴하는 공정과; 불투명하고 양극산화가능한 금속을 상기 투명 도전막상에 증착, 패턴하는 공정과; 상기 금속을 양극산화시킴으로써 양극 산화막을 형성하는 공정과; 절연막층과, 반도체층과, 오믹 콘택층을 상기 기판상에 전면 증착하고, 섬상으로 게이트 라인상에 패턴하는 공정과; 소오스 전극 및 드레인 전극 및 신호라인을 금속층으로 증착, 패턴하는 공정과; 상기 소오스 전극 및 드레인 전극을 마스크로 하여 액티브상의 오믹 콘택층을 식각하는 공정과; 화소전극을 형성하기 위하여 투명도전막을 증착하고 패턴화시키는 공정과; 패시베이션막을 증착하는 공정으로 구성되며; 게이트 라인과 저장 커패시터의 하부 전극을 투명 도전전극으로 사용하고, 게이트 형성후에 전면 양극산화가 가능한 메탈을 증착하여 전면 양극산화시킴으로써 크로스오버 쇼트의 문제를 해결할 수 있고, 또한 디바이스가 있는 부분의 평탄화를 가능하게 함으로써 액정공정의 러빙문제를 해결할 수 있는 효과를 가진 개구율 향상을 위한 액정표시장치의 제조방법에 관한 것.Depositing and patterning a transparent conductive film on a glass substrate in the form of a ladder as a first electrode of a gate line and a capacitor; Depositing and patterning an opaque and anodizable metal on the transparent conductive film; Forming an anodic oxide film by anodizing the metal; Depositing an insulating film layer, a semiconductor layer, and an ohmic contact layer over the substrate, and patterning the pattern on a gate line on an island; Depositing and patterning the source electrode, the drain electrode, and the signal line with a metal layer; Etching the ohmic contact layer of the active phase using the source electrode and the drain electrode as a mask; Depositing and patterning a transparent conductive film to form a pixel electrode; A passivation film is deposited; The bottom electrode of the gate line and the storage capacitor is used as a transparent conductive electrode, and after the gate is formed, the front anodization metal is deposited and the front anodization can be solved. The present invention relates to a method for manufacturing a liquid crystal display device for improving the aperture ratio, which has an effect of solving the rubbing problem of the liquid crystal process by making it possible.

Description

개구율 향상을 위한 액정표시장치 및 그 제조방법Liquid crystal display for improving aperture ratio and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 TFT액티브 매트릭스 방식의 액정표시장치를 유리기판쪽에서 본 평면도이고,1 is a plan view of a conventional TFT active matrix type liquid crystal display device seen from a glass substrate side,

제2도는 제1도의 A-A선을 자른 부분적인 단면도이고,2 is a partial cross-sectional view taken along the line A-A of FIG.

제3도~제8도는 이 발명의 제1실시예에 따른 개구율 향상을 위한 액정표시장치의 제조공정을 나타낸 평면도이고,3 to 8 are plan views showing the manufacturing process of the liquid crystal display for improving the aperture ratio according to the first embodiment of the present invention,

Claims (7)

유리기판상에 수평방향으로 복수개의 사다리꼴 형태의 게이트 라인 및 게이트 전극이 투명 도전막으로 형성되고, 상기 투명 도전막의 상부 일부분이 불투명 메탈로 형성되어 있고, 상기 게이트 라인과 수직되게 복수의 신호라인이 형성되고 있고, 상기 게이트 전극상에 신호전극과 연결되는 소오스 전극과, 화소전극과 연결되는 드레인 전극으로 구성되는 박막 트랜지스터 소자가 형성되어 있고, 상기 화소전극은 상기 사다리꼴 형태의 게이트 라인의 내측 일부를 따라 절연막을 매개로 오버랩되도록 하는 것을 특징으로 하는 개구율 향상을 위한 액정표시장치.A plurality of trapezoidal gate lines and gate electrodes are formed of a transparent conductive film in a horizontal direction on a glass substrate, and an upper portion of the transparent conductive film is formed of an opaque metal, and a plurality of signal lines are formed perpendicular to the gate line. And a thin film transistor element including a source electrode connected to a signal electrode and a drain electrode connected to a pixel electrode on the gate electrode, wherein the pixel electrode is formed along an inner portion of the trapezoidal gate line. Liquid crystal display for improving the aperture ratio, characterized in that overlapping the insulating film. 제 1항에 있어서, 상기 불투명 메탈은 상기 게이트 전극부 및 신호배선과 인정되어 형성된 상기 사다리꼴 형태의 게이트 라인의 수직 방향에만 형성되고, 화소의 가장자리의 광차단막으로 사용되는 것을 특징으로 하는 개구을 향상을 위한 액정표시장치.The opening of claim 1, wherein the opaque metal is formed only in a vertical direction of the trapezoidal gate line formed by being recognized with the gate electrode portion and the signal wiring, and used as a light blocking film at an edge of the pixel. Liquid crystal display device. 유리기판상에, 게이트 라인 및 커패시터의 제1전극으로서 사다리 형태로 투명 도전막을 증착하고 사진 식각법으로 패턴하는 공정과, 다음에, 불투명하고 양극산화가능한 금속을 상기 투명 도전막상에 증착하고 사진식각법으로 패턴하는 공정과, 다음에, 상기 금속을 양극산화시킴으로써 양극 산화막을 형성하는 공정과, 다음에, 절연막층과, 반도체층과, 오믹 콘택층을 상기 기판상에 전면 증착하는 공정과, 다음에, 상기 반도체층 및 오믹 콘택층을 섬상으로 상기 게이트 라인상에 사진식각법으로 패턴하는 공정과, 다음에, 소오스 전극 및 드레인 전극 및 신호라인을 금속층으로 증착하고 패팅히는 공정과, 다음에, 상기 소오스 전극 및 드레인 전극을 마스크로 하여 액티브상의 오믹 콘택층을 식각하는 공정과, 다음에, 화소전극을 형성하기 위하여 투명 도전막을 증착하고 패턴화시키는 공정과, 다음에, 패시베이션막을 증착하는 공정으로 이루어지는 것을 특징으로 하는 개구율 향상을 위한 액정표시장치의 제조방법.Depositing a transparent conductive film in a ladder form as a first electrode of a gate line and a capacitor on a glass substrate and patterning the same by photolithography; and then depositing an opaque and anodizable metal on the transparent conductive film and performing photolithography. A step of patterning the film, followed by a step of forming an anodic oxide film by anodizing the metal, followed by full deposition of an insulating film layer, a semiconductor layer, and an ohmic contact layer on the substrate, and then Patterning the semiconductor layer and the ohmic contact layer on an island with a photolithography method on an island, then depositing and patterning a source electrode, a drain electrode, and a signal line with a metal layer; Etching the active ohmic contact layer using the source electrode and the drain electrode as a mask, and subsequently forming a pixel electrode A method of manufacturing a liquid crystal display device for improving the aperture ratio, comprising a step of depositing and patterning a bright conductive film and then depositing a passivation film. 제3항에 있어서, 상기 반도체층은 비정질 실리콘(a-Si)으로 이루어지는 것을 특징으로 하는 개구율 향상을 위한 액정표시장치의 제조방법.The method of claim 3, wherein the semiconductor layer is made of amorphous silicon (a-Si). 제3항에 있어서, 상기 오믹 콘택층은 N형으로 도우프된 비정질 실리콘막으로 이루어지는 것을 특징으로 하는 개구율 향상을 위한 액정표시장치의 제조방법.4. The method of claim 3, wherein the ohmic contact layer is formed of an amorphous silicon film doped with an N-type. 제3항에 있어서, 상기 패시베이션막은 질화 실리콘막으로 이루어지는 것을 특징으로 하는 개구율 향상을 위한 액정표시장치의 제조방법.4. The method of claim 3, wherein the passivation film is formed of a silicon nitride film. 제3항에 있어서, 상기 절연막층은 질화 실리콘막으로 이루어지는 것을 특징으로 하는 개구율 향상을 위한 액정표시장치의 제조방법.4. The method of claim 3, wherein the insulating film layer is made of a silicon nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014187A 1994-06-22 1994-06-22 Liquid crystal display device and its manufacturing method for aperture ratio improvement KR0124976B1 (en)

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KR1019940014187A KR0124976B1 (en) 1994-06-22 1994-06-22 Liquid crystal display device and its manufacturing method for aperture ratio improvement
US08/493,000 US5663575A (en) 1994-06-22 1995-06-21 Liquid crystal display device providing a high aperture ratio

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100273848B1 (en) * 1996-09-30 2000-12-15 김영남 Electrode of pdp
WO2003036374A1 (en) * 2001-09-26 2003-05-01 Samsung Electronics Co., Ltd. Thin film transistor array panel for liquid crystal display and method for manufacturing the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100752207B1 (en) * 2000-01-07 2007-08-28 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Device
JP5771365B2 (en) 2009-11-23 2015-08-26 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． Medium and small liquid crystal display
KR101113354B1 (en) 2010-04-16 2012-02-29 삼성모바일디스플레이주식회사 Display device and fabrication method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100273848B1 (en) * 1996-09-30 2000-12-15 김영남 Electrode of pdp
WO2003036374A1 (en) * 2001-09-26 2003-05-01 Samsung Electronics Co., Ltd. Thin film transistor array panel for liquid crystal display and method for manufacturing the same
CN1325984C (en) * 2001-09-26 2007-07-11 三星电子株式会社 Thin film transistor array substrate of liquid crystal display device and producing method thereof

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