WO2003036374A1 - Thin film transistor array panel for liquid crystal display and method for manufacturing the same - Google Patents

Thin film transistor array panel for liquid crystal display and method for manufacturing the same Download PDF

Info

Publication number
WO2003036374A1
WO2003036374A1 PCT/KR2002/000334 KR0200334W WO03036374A1 WO 2003036374 A1 WO2003036374 A1 WO 2003036374A1 KR 0200334 W KR0200334 W KR 0200334W WO 03036374 A1 WO03036374 A1 WO 03036374A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
storage capacitor
line assembly
lines
thin film
Prior art date
Application number
PCT/KR2002/000334
Other languages
French (fr)
Inventor
Chang-Hun Lee
Nam-Hung Kim
Hak-Sun Chang
Jae-Jin Lyu
Original Assignee
Samsung Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR2001/59637 priority Critical
Priority to KR1020010059637A priority patent/KR20030026588A/en
Priority to KR1020010077838A priority patent/KR100840318B1/en
Priority to KR2001/77838 priority
Application filed by Samsung Electronics Co., Ltd. filed Critical Samsung Electronics Co., Ltd.
Publication of WO2003036374A1 publication Critical patent/WO2003036374A1/en
Priority claimed from US11/697,122 external-priority patent/US7990484B2/en

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306Circuit arrangements or driving methods for the control of single liquid crystal cells
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F2001/136295Materials; Compositions; Methods of manufacturing

Abstract

In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

Description

THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel for a liquid crystal display, and a method for manufacturing the same.

(b) Description of the Related Art

Generally, a liquid crystal display has two substrates with electrodes, and a liquid crystal layer sandwiched between the two substrates. Voltages are applied to the electrodes so that the liquid crystal molecules in the liquid crystal layer are re-oriented to thereby control the light transmission. The electrodes may be all formed at one of the substrates. One of the substrates is called the "thin film transistor array panel", and the other is called the "color filter substrate."

The thin film transistor array panel has a plurality of gate lines, data lines crossing over the gate lines while defining pixel regions, thin film transistors formed at the respective pixel regions while being electrically connected to the gate and the data lines, and pixel electrodes electrically connected to the thin film transistors.

Storage capacitors are formed at the thin film transistor array panel to keep the voltage applied to the liquid crystal disposed between the two substrates in a stable manner. For that purpose, a storage capacitor line assembly is formed at the same layer as the gate lines such that it is overlapped with the pixel electrodes to thereby form storage capacitors. Meanwhile, the electrostatic capacitance of the storage capacitors should be increased to enhance the brightness of the display device or to make rapid response speed thereof. In this connection, it is necessary to enlarge the area of the storage capacitor line assembly, but this causes decreased aperture or opening ratio.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a thin film transistor array panel for a liquid crystal display which involves storage capacitors with increased electrostatic capacitance while bearing a reasonable aperture ratio.

This and other objects may be achieved by a thin film transistor array panel for a liquid crystal display where the storage capacitor line assembly is formed at the same layer as the data lines, or the thickness of the insulating layer for the storage capacitors is minimized. According to one aspect of the present invention, the thin film transistor array panel includes an insulating substrate, and a gate line assembly formed on the insulating substrate and including gate lines, and gate electrodes. A gate insulating layer covers the gate line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly is formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines crossing over the gate lines, source electrodes connected to the data lines and the semiconductor pattern, and drain electrodes facing the source electrodes and connected to the semiconductor pattern. Storage capacitor electrode lines are formed between the neighboring data lines while crossing over the gate lines. A passivation layer covers the data line assembly, the storage capacitor electrode lines and the semiconductor pattern while bearing contact holes exposing the drain electrodes. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes through the contact holes. The pixel electrodes are overlapped with the storage capacitor electrode lines.

The thin film transistor array panel may further include a common interconnection line commonly interconnecting the storage capacitor electrode lines. The common interconnection line may be formed with the same material as the pixel electrodes or the gate lines while crossing over the data lines in an insulated manner.

The passivation layer has a plurality of contact holes exposing the storage capacitor electrode lines, and the common interconnection line is connected to the storage capacitor electrode lines through the contact holes. A subsidiary interconnection line may be connected to the storage capacitor electrode lines. The storage capacitor electrode lines and the subsidiary interconnection line are formed with the same material.

Gate pads are formed at one-sided end portions of the gate lines, and data pads are formed at one-sided end portions of the data lines. First contact holes are formed at the passivation layer and the gate insulating layer while exposing the gate pads, and second contact holes are formed at the passivation layer while exposing the data pads. Subsidiary gate and data pads are connected to the gate and the data pads through the first and the second contact holes. In addition to the above-structured thin film transistor array panel, the liquid crystal display includes a counter substrate facing the thin film transistor array panel, and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel. The liquid crystal display has storage capacitors with an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal capacitor having the liquid crystal layer by 90% or more.

According to another aspect of the present invention, the thin film transistor array panel includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns, respectively. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the

storage capacitor line assembly.

The storage capacitor line assembly has storage capacitor electrode

lines proceeding parallel to the gate lines, and storage capacitor electrode

patterns connected to the storage capacitor electrode lines. The storage capacitor electrode patterns are overlapped with the storage capacitor

conductive patterns to thereby form the first storage capacitors, and the storage capacitor electrode lines are overlapped with the pixel electrodes to

thereby form the second storage capacitors. The storage capacitor electrode patterns are formed within pixel regions defined by the gate lines and the data lines. The storage capacitor electrode patterns are formed with a bar shape along the data lines while being overlapped with peripheral portions of the pixel electrodes.

In addition to the above-structured thin film transistor array panel, the liquid crystal display includes a counter substrate facing the thin film transistor array panel, and a liquid crystal layer sandwiched between the thin

film transistor array panel and the counter panel. The first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

According to still another aspect of the present invention, the thin film

transistor array panel includes an insulating substrate, and a gate line

assembly formed on the" insulating substrate. The gate line assembly has

first gate lines, gate electrodes connected to the first gate lines, and second

gate lines spaced apart from the first gate lines with a predetermined

distance. A gate insulating layer covers the gate line assembly. A semiconductor pattern is formed on the gate insulating layer while being overlapped with the gate electrodes. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the second gate lines to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns, respectively. Pixel electrodes are formed at the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes are partially overlapped with the second gate lines to thereby form second storage capacitors.

In addition to the above-structured thin film transistor array panel, the liquid crystal display includes a counter substrate facing the thin film transistor array panel, and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel. The first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

According to still another aspect of the present invention, the thin film transistor array panel includes an insulating substrate, and a gate line assembly and storage capacitor electrode lines formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A

gate insulating layer covers the gate line assembly and the storage capacitor

electrode lines. First contact holes are formed at the gate insulating layer

while exposing the storage capacitor electrode lines. A semiconductor

pattern is formed on the gate insulating layer while being overlapped with the

gate electrodes. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the

semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are connected to the storage capacitor electrode lines through the first contact holes. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. Second contact holes are formed at the passivation layer while exposing the drain electrodes. Pixel electrodes are formed at the passivation layer while being connected to the drain electrodes through the second contact holes. The pixel electrodes are overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially

overlapped with the storage capacitor electrode lines to thereby form second storage capacitors.

The storage capacitor electrode lines proceed parallel to the gate

lines, and the storage capacitor conductive patterns are overlapped with the

storage capacitor electrode lines. The storage capacitor conductive

patterns are formed within pixel regions defined by the gate lines and the

data lines. The storage capacitor electrode patterns are formed with a bar

shape along the data lines while being overlapped with peripheral portions of the pixel electrodes.

In addition to the above-structured thin film transistor array panel, the liquid crystal display includes a counter substrate facing the thin film transistor array panel, and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel. The first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

According to still another aspect of the present invention, the thin film transistor array panel includes an insulating substrate, and a gate line assembly formed on the insulating substrate. The gate line assembly has first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance. A gate insulating layer covers the gate line assembly. First contact holes are formed at the gate insulating layer while partially exposing the second gate lines. A semiconductor pattern is formed on the gate insulating layer while being overlapped with the gate electrodes. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are connected to the second gate lines through the first contact holes. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. Second contact holes are formed at the passivation layer while exposing the drain electrodes. Pixel electrodes are formed at the passivation layer while being connected to the drain electrodes through the second contact holes. The pixel electrodes are overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the second gate lines to thereby form second storage capacitors.

In addition to the above-structured thin film transistor array panel, the liquid crystal display includes a counter substrate facing the thin film transistor array panel, and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel. The first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

According to still another aspect of the present invention, in a method of fabricating a thin film transistor array panel, a gate line assembly and a storage capacitor line assembly are formed on an insulating substrate such that the gate line assembly has gate lines and gate electrodes. A gate insulating layer is formed on the substrate such that it covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer is formed on the substrate such that it covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer such that they expose the drain electrodes and the storage capacitor conductive patterns, respectively. Pixel electrodes are formed on the passivation layer such that they are connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes while forming second storage capacitors in association with parts of the storage capacitor lines assembly.

The storage capacitor line assembly has storage capacitor electrode lines proceeding parallel to the gate lines, and storage capacitor electrode patterns connected to the storage capacitor electrode lines.

According to still another aspect of the present invention, in a method of fabricating a thin film transistor array panel, a gate line assembly is formed on an insulating substrate such that it has first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance while proceeding parallel to the first gate lines. A gate insulating layer is formed on the substrate such that it covers the gate line assembly. A semiconductor pattern is formed on the gate insulating layer such that it is overlapped with the gate electrodes. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are partially overlapped with the second gate lines to thereby form first storage capacitors. A passivation layer is formed on the substrate such that it covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive patterns, respectively. Pixel electrodes are formed on the passivation layer such that they are connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes while forming second storage capacitors in association with parts of the second gate lines.

According to still another aspect of the present invention, in a method of fabricating a thin film transistor array panel, a gate line assembly and storage capacitor electrode lines are formed on an insulating substrate such that the gate line assembly has gate lines and gate electrodes. A gate insulating layer is formed on the substrate such that it covers the gate line assembly and the storage capacitor electrode lines. First contact holes are formed at the gate insulating layer such that they expose the storage capacitor electrode lines. A semiconductor pattern is formed on the gate insulating layer such that it is overlapped with the gate electrodes. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are connected to the storage capacitor electrode lines through the first contact holes. A passivation layer is formed on the substrate such that it covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. Second contact holes are formed at the passivation layer such that they expose the drain electrodes. Pixel electrodes are formed on the passivation layer such that they are connected to the drain electrodes through the second contact holes. The pixel electrodes are overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the storage capacitor electrode lines to thereby form second storage capacitors.

According to still another aspect of the present invention, in a method of fabricating a thin film transistor array panel, a gate line assembly is formed on an insulating substrate such that it has first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance while proceeding parallel to the first gate lines. A gate insulating layer is formed on the substrate such that it covers the gate line assembly. First contact holes are formed at the gate insulating layer such that they partially expose the second gate lines. A semiconductor pattern is formed on the gate insulating layer such that it is overlapped with the gate electrodes. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are connected to the second gate lines through the first contact holes. A passivation layer is formed on the substrate such that it covers the data line assembly, the storage capacitor conductive patterns and the semiconductor . pattern. Second contact holes are formed at the passivation layer such that they expose the drain electrodes. Pixel electrodes are formed on the passivation layer such that they are connected to the drain electrodes

through the second contact holes. The pixel electrodes are overlapped with

the storage capacitor conductive patterns to thereby form first storage

capacitors while being partially overlapped with the second gate lines to

thereby form second storage capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the

attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or the similar components, wherein:

Fig. 1 is a plan view of a thin film transistor array panel according to a first preferred embodiment of the present invention;

Figs. 2 and 3 are cross sectional views of the thin film transistor array panel taken along the 11-11' line and the Ill-Ill' line of Fig. 1 ;

Fig. 4 illustrates the layout of gate lines, data lines and storage

capacitor electrode lines at the thin film transistor array panel shown in Fig. 1 ;

Fig. 5A illustrates the first step of fabricating the thin film transistor

array panel shown in Fig. 1 ; Figs. 5B and 5C are cross sectional views of the thin film transistor array panel taken along the VB-VB' line and the VC-VC line of Fig. 5A;

Fig. 6A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 5A;

Figs. 6B and 6C are cross sectional views of the thin film transistor array panel taken long the VIB-VIB' line and the VIC-VIC line of Fig. 6A;

Fig. 7A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 6A;

Figs. 7B and 7C are cross sectional views of the thin film transistor array panel taken long the VIIB-VIIB' line and the VIIC-VIIC line of Fig. 7A;

Fig. 8 is a plan view of a thin film transistor array panel according to a

second preferred embodiment of the present invention;

Fig. 9 is a cross sectional view of the thin film transistor array panel taken along the IX-IX' line of Fig. 8;

Fig. 10A illustrates the first step of fabricating the thin film transistor

array panel shown in Fig. 8;

Figs. 10B is a cross sectional view of the thin film transistor array panel taken long the XBb-XB' line of Fig. 10A;

Fig. 1 1 A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 10A;

Fig. 1 1 B is a cross sectional view of the thin film transistor array panel taken long the XIB-XIB' line of Fig. 1 1 A;

Fig. 12A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 1 1 A;

Fig. 12B is a cross sectional view of the thin film transistor array panel taken long the XIIB-XIIB' line of Fig. 12A;

Fig. 13A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 12A;

Fig. 13B is a cross sectional view of the thin film transistor array panel taken long the XIIIB-XIIIB' line of Fig. 13A; Fig. 14 is a plan view of a thin film transistor array panel according to

a third preferred embodiment of the present invention;

Fig. 15 is a cross sectional view of the thin film transistor array panel taken along the XV-XV line of Fig. 14;

Fig. 16 is a plan view of a thin film transistor array panel according to a fourth preferred embodiment of the present invention;

Fig. 17 is a cross sectional view of the thin film transistor array panel taken long the XVII-XVII' line of Fig. 16;

Fig. 18 is a plan view of a thin film transistor array panel according to a fifth preferred embodiment of the present invention;

Fig. 19 is a cross sectional view of the thin film transistor array panel taken long the XIX-XIX' line of Fig. 18;

Fig. 20A illustrates the first step of fabricating the thin film transistor array panel shown in Fig. 18; Fig. 20B is a cross sectional view of the thin film transistor array panel taken long the XXB-XXB' line of Fig. 20A;

Fig. 21 A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 20A;

Fig. 21 B is a cross sectional view of the thin film transistor array panel taken long the XXIB-XXIB' line of Fig. 21 A;

Fig. 22A illustrates the step of fabricating the thin film transistor array

panel following the step illustrated in Fig. 21 A;

Fig. 22B is a cross sectional view of the thin film transistor array panel taken long the XXIIB-XXIIB' line of Fig. 22A;

Fig. 23A illustrates the step of fabricating the thin film transistor array panel following the step illustrated in Fig. 22A;

Fig. 23B is a cross sectional view of the thin film transistor array panel taken long the XXIIIB-XXIIIB' line of Fig. 23A;

Fig. 24A illustrates the step of fabricating the thin film transistor array panel following the step illustrated in Fig. 23A;

Fig. 24B is a cross sectional view of the thin film transistor array panel taken long the XXIVB-XXIVB' line of Fig. 24A;

Fig. 25 is a plan view of a thin film transistor array panel according to a sixth preferred embodiment of the present invention; Fig. 26 is a cross sectional view of the thin film transistor array panel taken long the XXVI-XXVI' line of Fig. 25;

Fig. 27 is a plan view of a thin film transistor array panel according to a seventh preferred embodiment of the present invention;

Fig. 28 is a cross sectional view of the thin film transistor array panel taken long the XXVI 11 -XXVIII' line of Fig. 27; and

Fig. 29 illustrates a waveform curve of the response speed in a liquid crystal display.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be explained with reference to the accompanying drawings.

Fig. 1 is a plan view of a thin film transistor array panel for a liquid crystal display according to a first preferred embodiment of the present invention, and Figs. 2 and 3 are cross sectional views of the thin film transistor array panel taken along the ll-ll' line and the Ill-Ill' line of Fig. 1. A gate line assembly is formed on an insulating substrate 10 with a conductive material such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride, and molybdenum

nitride while bearing a thickness of 1000-3500 A. The gate line assembly

includes gate lines 22 proceeding in the horizontal direction, gate pads 24 connected to the one-sided ends of the gate lines 22 while electrically contacting external driving circuits (not shown), and gate electrodes 26 being parts of the gate lines 22 while forming thin film transistors with other electrode components. The gate line assembly may have a multiple-layered structure where one layer is formed with a low resistance metallic material, and the other layer with a material bearing a good contact characteristic with other materials.

A gate insulating layer 30 with a thickness of 2,500-4,500A is

formed on the insulating substrate 10 with silicon nitride or silicon oxide while covering the gate line assembly.

A semiconductor pattern 42 with a thickness of 800-1500 A is

formed on the gate insulating layer 30 with amorphous silicon while being overlapped with the gate electrodes 26. Ohmic contact patterns 55 and 56

with a thickness of 500-800 A are formed on the semiconductor pattern 42

with amorphous silicon where n type impurities are doped at high concentration.

A data line assembly and storage capacitor electrode lines 69 are formed on the ohmic contact patterns 55 and 56, and the gate insulating 03/036374

18 layer 30 with a conductive material such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride and

molybdenum nitride while bearing a thickness of 500-3500 A. The data line

assembly includes data lines 62 proceeding in the vertical direction while crossing over the gate lines 22 to define pixel regions, data pads 64 connected to the one-sided ends of the data lines 62 while electrically contacting external driving circuits, source electrodes 65 connected to the data lines 62 while being extended over the ohmic contact pattern 55, and drain electrodes 66 facing the source electrodes 65 while being placed over the other ohmic contact pattern 56. The drain electrodes 66 are extended over the gate insulating layer 30 within the pixel regions.

The storage capacity electrode lines 69 are placed at the same plane as the data line assembly while proceeding in the vertical direction such that they are alternately arranged with the data lines 62. The storage capacity electrode lines 69 are overlapped with pixel electrodes 82 to thereby form storage capacitors.

The data line assembly may have a multiple-layered structure where at least one layer is formed with a low resistance metallic material.

A passivation layer 70 covers the data line assembly, the storage capacitor electrode lines 69 and the semiconductor pattern 42 while bearing

a thickness of 500-2000 . The passivation layer 70 is formed with an

insulating material such as silicon nitride and silicon oxide.

First and second contact holes 72 and 74 are formed at the passivation layer 70 while exposing the drain electrodes 66 and the data pads 64. Third contact holes 76 are formed at the passivation layer 70 while

exposing the gate pads 24 together with the gate insulating layer 30.

Furthermore, fourth contact holes 79 are formed at the passivation layer 70

while exposing the end portions of the storage capacitor electrode lines 69 sided with the data pads 64.

Pixel electrodes 82 are formed on the passivation layer 70 to receive

picture signals and generate electric fields together with a common electrode (not shown) of the counter panel. The pixel electrodes 82 are electrically connected to the drain electrodes 66 through the first contact holes 72.

The pixel electrodes 82 are overlapped with the storage capacitor electrode lines 69 while interposing the passivation layer 70 to thereby form storage capacitors. As the passivation layer 70 disposed between the pixel electrodes 82 and the storage capacitor electrode lines 69 bears a thin thickness, the resulting storage capacitors bear a great electrostatic capacitance even when the storage capacitor electrode lines 69 bear a narrow width.

Subsidiary data pads 84 and subsidiary gate pads 86 are formed on

the passivation layer 70 while being connected to the data pads 64 and the gate pads 24 through the second and the third contact holes 74 and 76.

Furthermore, a common interconnection line 88 is formed external to the

display area while proceeding parallel to the gate lines 22. The display area

refers to the sum of the pixel regions. The common interconnection line 88 interconnects all of the storage capacitor electrode lines 69 through the fourth

contact holes 79.

The pixel electrodes 82, the subsidiary data pads 84, the subsidiary gate pads 86 and the common interconnection line 88 are formed at the same plane with a transparent conductive material such as ITO and IZO.

The common interconnection line 88 may be formed with the same material as the gate line assembly during the process of forming the gate line assembly. In this case, a plurality of contact holes are formed at the gate insulating layer 30 while exposing the common interconnection line 88. The plurality of storage capacitor electrode lines 69 contact the common interconnection line 88 through the contact holes formed at the gate insulating layer 30. Fig. 4 illustrates the arrangement of the gate lines, the data lines and the storage capacitor electrode lines at the thin film transistor array panel shown in Fig. 1.

As shown in Fig. 4, the plurality of gate lines 22 proceed in the horizontal direction parallel to each other, and the plurality of data lines 62 proceed in the vertical direction parallel to each other. The data lines 62 cross over the gate lines 22 while defining the pixel regions. The display area 110 refers to the sum of the pixel regions.

The one-sided end portions of the data lines 62 being the data pads are electrically connected to data driving circuits 300 to receive data signals from them. Similarly, the one-sided end portions of the gate lines 22 being the gate pads are electrically connected to gate driving circuits (not shown) to receive gate signals from them.

The storage capacitor electrode lines 69 are alternately arranged with the data lines 62. The storage capacitor electrode lines 69 are connected to each other by way of a subsidiary interconnection line 61 placed external to the display area 1 10. It is preferable that the storage

capacitor electrode lines 69 and the subsidiary interconnection line 61 are

formed with the same material while being commonly interconnected.

The common interconnection line 88 is placed at the ends of the

storage capacitor electrode lines 69 sided with the data driving circuits while

interconnecting all of the storage capacitor electrode lines 69. It is preferable that the common interconnection line 88 is formed with the same

material as the pixel electrodes 82 or the gate line assembly. This is to prevent the common interconnection line 88 from being short circuited with the portions of the data lines 62 connected to the data driving circuits 300 external to the display area 1 10.

The storage capacitor electrode lines 69 are electrically connected to the data driving circuits 300 to receive common electrode voltages from them.

A method of fabricating the thin film transistor array panel will be now explained with reference to Figs. 5A to 7C as well as Figs. 1 to 4.

As shown in Figs. 5A to 5C, a gate line assembly layer is deposited onto an insulating substrate 10, and patterned through photolithography to

thereby form a gate line assembly. The gate line assembly includes gate

lines 22, gate pads 24, and gate electrodes 26. Thereafter, a gate insulating layer 30 based on an insulating material

such as silicon nitride is deposited onto the insulating substrate 10 such that

it covers the gate line assembly.

An amorphous silicon layer and a conductive type impurities-doped

amorphous silicon layer are sequentially deposited onto the gate insulating

layer 30, and patterned through photolithography to thereby form a semiconductor pattern 42 and an ohmic contact pattern 52.

As shown in Figs. 6A to 6C, a metallic layer is deposited onto the entire surface of the substrate, and patterned through photolithography to thereby form a data line assembly and storage capacitor electrode lines 69. The data line assembly includes data lines 62, data pads 64, source electrodes 65, and drain electrodes 66. The storage capacitor electrode lines 69 are alternately arranged with the data lines 62.

The ohmic contact pattern 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to thereby separate it into a first portion 55 contacting the source electrode 65, and a second portion 56 contacting the drain electrode 66.

As shown in Figs. 7A to 7C, a passivation layer 70 covers the data line assembly, the storage capacitor electrode lines 69, and the semiconductor pattern 42. The passivation layer 70 is formed with silicon nitride while bearing a thin thickness. In consideration of the electrostatic capacitance of the storage capacitors to be formed, it is preferable that the thickness of the passivation layer 70 is controlled in an appropriate manner.

The passivation layer 70 and the gate insulating layer 30 are patterned through photolithography to thereby form first to fourth contact holes 72, 74, 76 and 79.

As shown in Figs. 1 to 3, a transparent conductive layer based on ITO or IZO is deposited onto the entire surface of the substrate 10.

The transparent conductive layer is patterned through photolithography to thereby form pixel electrodes 82, subsidiary data pads 84, subsidiary gate pads 86, and a common interconnection line 88. The pixel electrodes 82 are connected to the drain electrodes 66 through the first

contact holes 72. The subsidiary data and gate pads 84 and 86 are

connected to the data and gate pads 64 and 24 through the second and the

third contact holes 74 and 76. The common interconnection line 88

interconnects all of the storage capacitor electrode lines 69 through the fourth contact holes 79.

The common interconnection line 88 may be formed with the same

material as the gate line assembly. For that purpose, the common interconnection line is formed during the process of forming the gate line assembly while being followed by the formation of the gate insulating layer 30. A plurality of contact holes exposing the common interconnection line are then formed at the gate insulating layer 30. The storage capacitor electrode lines 69 are formed during the process of forming the data line assembly. In this process, the storage capacitor electrode lines 69 are connected to the common interconnection line through the contact holes.

As described above, the storage capacitor electrode lines are formed at the same plane as the data lines such that they are overlapped with the pixel electrodes while interposing the passivation layer bearing a thin

thickness to thereby form storage capacitors. Alternatively, the storage capacitors may be formed using a gate

insulating layer instead of the passivation layer.

Fig. 8 is a plan view of a thin film transistor array panel according to a

second preferred embodiment of the present invention, and Fig. 9 is a cross sectional view of the thin film transistor array panel taken along the IX-IX' line

of Fig. 8. A gate line assembly and a storage capacitor line assembly are formed on an insulating substrate 10 with a conductive material such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride, and molybdenum nitride while bearing a thickness of

1000-3500 A.

The gate line assembly includes gate lines 22 proceeding in the horizontal direction, gate pads 24 formed at the one-sided end portions of the gate lines 22 while electrically contacting external driving circuits (not shown), and gate electrodes 26 being parts of the gate lines 22 while forming thin film transistors with other components.

The storage capacitor line assembly includes rectangular-shaped storage capacitor electrode patterns 28 disposed between the neighboring gate lines 22, and storage capacitor electrode lines 29 connected to the storage capacitor electrode patterns in the neighboring pixel regions while proceeding in the horizontal direction parallel to the gate lines 22.

The gate line assembly and the storage capacitor line assembly may have a multiple-layered structure where at least one layer is formed with a low resistance metallic material.

A gate insulating layer 30 with a thickness of 2500-4500A is formed

on the insulating substrate 10 with silicon nitride or silicon oxide while covering the gate line assembly and the storage capacitor line assembly.

A semiconductor pattern 42 with a thickness of 800-1500 A is

formed on the gate insulating layer 30 with amorphous silicon while being overlapped with the gate electrodes 26. Ohmic contact patterns 55 and 56 with a thickness of 500-800 A are formed on the semiconductor pattern 42

with amorphous silicon where n type impurities are doped at high concentration.

A data line assembly and storage capacitor conductive patterns 68 are formed on the ohmic contact patterns 55 and 56 and the gate insulating layer 30 with a conductive material such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride and

molybdenum nitride while bearing a thickness of 500-3500 A.

The data line assembly includes data lines 62 proceeding in the vertical direction while crossing over the gate lines 22 to define pixel regions, data pads 64 formed at the one-sided end portions of the data lines 62 while electrically contacting external driving circuits, source electrodes 65 connected to the data lines 62 while being extended over the ohmic contact pattern 55, and drain electrodes 66 facing the source electrodes 65 while being placed over the other ohmic contact pattern 56. The drain electrodes 66 are extended over the gate insulating layer 30 within the pixel regions.

The storage capacity conductive patterns 68 are placed at the same plane as the data line assembly while bearing an island shape such that they are overlapped with the storage capacitor electrode patterns 28 while interposing the gate insulating layer 30 to thereby form storage capacitors. The storage capacitor conductive patterns 68 are electrically connected to pixel electrodes 82 to be described later to receive picture signal voltages.

The data line assembly and the storage capacitor conductive patterns 68 may have a multiple-layered structure where at least one layer is formed with a low resistance metallic material.

A passivation layer 70 covers the data line assembly, the storage capacitor conductive patterns 68 and the semiconductor pattern 42 while

bearing a thickness of 500-2000 A. The passivation layer 70 is formed with

5 an insulating material such as silicon nitride and silicon oxide.

First and second contact holes 72 and 74 are formed at the passivation layer 70 while exposing the drain electrodes 66 and the data pads 64. Third contact holes 76 are formed at the passivation layer 70 while exposing the gate pads 24 together with the gate insulating layer 30. 10 Furthermore, fourth contact holes 78 are formed at the passivation layer 70 while exposing the storage capacitor conductive patterns 68.

Pixel electrodes 82 are formed on the passivation layer 70 such that they are electrically connected to the drain electrodes 66 and the storage capacitor conductive patterns 68 through the first and the fourth contact holes 15 72 and 78.

Subsidiary data pads 84 and subsidiary gate pads 86 are formed on the passivation layer 70 while being connected to the data pads 64 and the gate pads 24 through the second and the third contact holes 74 and 76.

The pixel electrodes 82, the subsidiary data pads 84 and the 20 subsidiary gate pads 86 are formed with a transparent conductive material such as ITO and IZO.

The pixel electrodes 82 are overlapped with the storage capacitor line assembly while interposing the passivation layer 70 and the gate insulating layer 30 to thereby form storage capacitors. The pixel electrodes 82 are connected to the storage capacitor

conductive patterns 68. In this way, the storage capacitor conductive

patterns 68 form other storage capacitors in association with the storage

capacitor electrode patterns 28 while interposing the gate insulating layer 30.

In this case, as the thickness of the gate insulating layer 30 disposed

between the storage capacitor conductive patterns 68 and the storage

capacitor electrode patterns 28 is small, the electrostatic capacitance of the resulting storage capacitors becomes increased even with the same overlapping area compared to the overlapping of the storage capacitor electrode patterns 28 and the pixel electrodes 82. Consequently, the aperture ratio with respect to the storage capacity becomes enhanced.

A method of fabricating the thin film transistor array panel will be now explained with reference to Figs. 10A to 13B as well as Figs. 8 and 9.

As shown in Figs. 10A and 10B, a metallic layer is deposited onto an insulating substrate 10, and patterned through photolithography to thereby form a gate line assembly and a storage capacitor line assembly. The gate line assembly includes gate lines 22, gate pads 24, and gate electrodes 26. The storage capacitor line assembly includes storage capacitor electrode

patterns 28, and storage capacitor electrode lines 29. Thereafter, as shown in Figs. 1 1 A and 1 1 B, a gate insulating layer 30

based on an insulating material such as silicon nitride is deposited onto the

insulating substrate 10 such that it covers the gate line assembly and the

storage capacitor line assembly.

An amorphous silicon layer and a conductive type impurities-doped

amorphous silicon layer are sequentially deposited onto the gate insulating layer 30, and patterned through photolithography to thereby form a semiconductor pattern 42 and an ohmic contact pattern 52.

As shown in Figs. 12A and 12B, a metallic layer is deposited onto the entire surface of the substrate 10, and patterned through photolithography to thereby form a data line assembly, and storage capacitor conductive patterns

68. The data line assembly includes data lines 62, data pads 64, source electrodes 65, and drain electrodes 66. The storage capacitor conductive patterns 68 are overlapped with the storage capacitor electrode patterns 28.

The ohmic contact pattern 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to thereby separate it into a first portion 55 contacting the source electrode 65, and a second portion 56 contacting the drain electrode 66.

As shown in Figs. 13A and 13B, a passivation layer 70 is formed on the entire surface of the substrate 10 having the data line assembly, the storage capacitor conductive patterns 68 and the semiconductor pattern 42 with silicon nitride or silicon oxide. The passivation layer 70 and the gate insulating layer 30 are patterned through photolithography to thereby form first to fourth contact holes 72, 74, 76 and 78. The first contact holes 72, the second contact holes 74 and the fourth contact holes 78 are formed at the passivation layer 70 while exposing the drain electrodes 66, the data pads 64 and the storage capacitor conductive patterns 68, respectively. Furthermore, the third contact holes 76 are formed at the passivation layer 70 and the gate insulating layer 30 while exposing the gate pads 24.

As shown in Figs. 8 and 9, a transparent conductive layer based on ITO or IZO is deposited onto the entire surface of the substrate 10. The transparent conductive layer is patterned through photolithography to thereby form pixel electrodes 82, subsidiary data pads 84, and subsidiary gate pads 86. The pixel electrodes 82 are connected to the drain electrodes 66 and the storage capacitor conductive patterns 68 through the first and the fourth contact holes 72 and 78. The subsidiary data and gate pads 84 and 86 are connected to the data and gate pads 64 and 24 through the second and the third contact holes 74 and 76.

In this preferred embodiment, the storage capacitor conductive patterns 68 are placed at the pixel regions between the neighboring gate lines while bearing an island shape. Alternatively, the storage capacitor conductive patterns 68 may be formed at the periphery of the pixel regions while bearing a bar shape. In this case, the storage capacitor electrode patterns 28 for forming storage capacitors in association with the storage capacitor conductive patterns 68 are also formed with a bar shape. Fig. 14 is a plan view of a thin film transistor array panel according to a third preferred embodiment of the present invention, and Fig. 15 is a cross sectional view of the thin film transistor array panel taken along the XV-XV line of Fig. 14.

In this preferred embodiment, the storage capacitor electrode patterns 28 are placed at both peripheral sides of the pixel regions while bearing a bar shape. Of course, the respective storage capacitor electrode patterns 28 are connected to the storage capacitor electrode lines 29.

The storage capacitor conductive patterns 68 for forming storage capacitors in association with the storage capacitor electrode patterns 28 are overlapped with the storage capacitor electrode patterns 28 while interposing the gate insulating layer 30.

The fourth contact holes 78 through which the storage capacitor

conductive patterns 68 are connected to the pixel electrodes 82 are

established to partially expose the storage capacitor conductive patterns 68.

In this structure, the storage capacitor electrode lines 29 form

storage capacitors in association with the pixel electrodes 82 while interposing the gate insulating layer 30 and the passivation layer 70.

Furthermore, the storage capacitor electrode patterns 28 form storage capacitors in association with the storage capacitor conductive patterns 68 while interposing the gate insulating layer 30.

With such a structure, the electrostatic capacitance of the resulting storage capacitors becomes increased even with the same overlapping area compared to the case where the storage capacitor electrode patterns 28 are overlapped with only the pixel electrodes 82. Consequently, the aperture ratio with respect to the storage capacity becomes enhanced.

Furthermore, as the bar-shaped storage capacitor electrode patterns 28 or storage capacitor conductive patterns 68 are placed between the pixel electrodes 82 and the data lines 62, leakage of light between the pixel

electrodes 82 and the data lines 62 can be prevented.

In the second and third preferred embodiments of the present invention, the storage capacitor line assembly is formed in a separate

manner. Alternatively, parts of the gate lines may be utilized as the storage

capacitor electrodes.

Fig. 16 is a plan view of a thin film transistor array panel according to

a fourth preferred embodiment of the present invention, and Fig. 17 is a cross sectional view of the thin film transistor array panel taken along the XVII-XVII'

line of Fig. 16.

In this preferred embodiment, the pixel electrodes arranged at any one gate line are overlapped with parts of the previous gate line to form storage capacitors. That is, parts of the gate lines are used to form the desired storage capacitors without forming a storage capacitor line assembly in a separate manner.

As shown in Fig. 16, the pixel electrodes 82 at the nth gate line 22

(Gn) are overlapped with the (n-1)th gate line 22 (Gn-1) while being extended in its area.

The storage capacitor conductive patterns 68 are partially overlapped with the gate lines 22 while interposing the gate insulating layer 30. The storage capacitor conductive patterns 68 are placed at the same plane as the data line assembly. The fourth contact holes 78 exposing the storage capacitor conductive patterns 68 are formed at the passivation layer 70, and the pixel electrodes 82 at any one gate line 22 are connected to the storage capacitor conductive patterns 68 placed over the previous gate line 22 through the fourth contact holes 78.

The storage capacitor conductive patterns 68 are overlapped with the gate lines 22 while interposing the gate insulating layer 30 to thereby form storage capacitors. The storage capacitor conductive patterns 68 placed over the (n-1)th gate line 22 (Gn-1) receive the relevant signals from the pixel electrodes 82 at the nth gate line 22 (Gn).

In the above structure, the storage capacity becomes significantly increased compared to the case where the storage capacitors are formed only through overlapping the pixel electrodes 82 with the gate lines 22. Furthermore, as a separate storage capacitor line assembly is not needed, the aperture ratio can be further enhanced.

Fig. 18 is a plan view of a thin film transistor array panel according to a fifth preferred embodiment of the present invention, and Fig. 19 is a cross sectional view of the thin film transistor array panel taken along the XIX-XIX'

line of Fig. 18.

A gate line assembly and storage capacitor electrode lines 27 are formed on an insulating substrate 10 with a conductive material such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride, and molybdenum nitride while bearing a thickness of

1000-3500 A.

The gate line assembly includes gate lines 22 proceeding in the horizontal direction, gate pads 24 formed at the one-sided end portions of the gate lines 22 while electrically contacting external driving circuits (not shown), and gate electrodes 26 being parts of the gate lines 22 while forming thin film transistors with other electrode components.

The storage capacitor electrode lines 27 are placed between the neighboring gate lines 22 while proceeding in the horizontal direction parallel to the gate lines 22.

The gate line assembly and the storage capacitor electrode lines 27 may have a multiple-layered structure where at least one layer is formed with a low resistance metallic material.

A gate insulating layer 30 with a thickness of 2500-4500A is formed on the insulating substrate 10 with silicon nitride or silicon oxide while covering the gate line assembly and the storage capacitor electrode lines 27. First contact holes 32 are formed at the gate insulating layer 30 while exposing the storage capacitor electrode lines 27.

A semiconductor pattern 42 with a thickness of 800-1500 A is

formed on the gate insulating layer 30 with amorphous silicon while being overlapped with the gate electrodes 26. Ohmic contact patterns 55 and 56

with a thickness of 500-800 A are formed on the semiconductor pattern 42

with amorphous silicon where n type impurities are doped at high concentration.

A data line assembly and storage capacitor conductive patterns 67 are formed on the ohmic contact patterns 55 and 56 and the gate insulating layer 30 with a conductive material such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride and

molybdenum nitride while bearing a thickness of 500-3500 A.

The data line assembly includes data lines 62 proceeding in the vertical direction while crossing over the gate lines 22 to define pixel regions, data pads 64 connected to the one-sided ends of the data lines 62 while electrically contacting external driving circuits, source electrodes 65 protruded from the data lines 62 while being extended over the ohmic contact pattern 55, and drain electrodes 66 facing the source electrodes 65 while being placed over the other ohmic contact pattern 56. The drain electrodes 66 are extended over the gate insulating layer 30 within the pixel regions.

The storage capacity conductive patterns 67 are placed at the same plane as the data line assembly while being connected to the storage capacitor electrode lines 27 through the first contact holes 32. The storage capacitor conductive patterns 67 are overlapped with pixel electrodes 82 to be described later to thereby form storage capacitors. The storage capacitor conductive patterns 67 are connected to the storage capacitor electrode lines 27 to receive common voltages.

The data line assembly and the storage capacitor conductive patterns 67 may have a multiple-layered structure where at least one layer is formed with a low resistance metallic material. A passivation layer 70 covers the data line assembly, the storage capacitor conductive patterns 67 and the semiconductor pattern 42 while

bearing a thickness of 500-2000 A. The passivation layer 70 is formed with

an insulating material such as silicon nitride and silicon oxide.

Second and third contact holes 72 and 74 are formed at the passivation layer 70 while exposing the drain electrodes 66, and the data pads 64. Fourth contact holes 76 are further formed at the passivation layer

70 while exposing the gate pads 24 together with the gate insulating layer 30.

Pixel electrodes 82 are formed on the passivation layer 70 such that they are electrically connected to the drain electrodes 66 through the second contact holes 72.

Subsidiary data pads 84 and subsidiary gate pads 86 are formed on the passivation layer 70 while being connected to the data pads 64 and the gate pads 24 through the third and the fourth contact holes 74 and 76.

The pixel electrodes 82, the subsidiary data pads 84 and the subsidiary gate pads 86 are formed with a transparent conductive material such as ITO and IZO.

The pixel electrodes 82 are overlapped with the storage capacitor electrode lines 27 while interposing the passivation layer 70 and the gate insulating layer 30 to thereby form storage capacitors.

The pixel electrodes 82 are also overlapped with the storage capacitor conductive patterns 67 connected to the storage capacitor electrode lines 27 while interposing the passivation layer 70 to thereby form other storage capacitors. In this case, as the thickness of the passivation layer 70 disposed between the pixel electrodes 82 and the storage capacitor conductive patterns 67 is small, the electrostatic capacitance of the resulting storage capacitors becomes increased even with the same overlapping area compared to the overlapping of the storage capacitor electrode lines 27 and the pixel electrodes 82. Consequently, the aperture ratio with respect to the storage capacity becomes enhanced.

A method of fabricating the thin film transistor array panel will be now explained with reference to Figs. 20A to 24B as well as Figs. 18 and 19.

As shown in Figs. 20A and 20B, a metallic layer is deposited onto an insulating substrate 10, and patterned through photolithography to thereby form a gate line assembly and storage capacitor electrode lines 27. The gate line assembly includes gate lines 22, gate pads 24, and gate electrodes 26.

Thereafter, as shown in Figs. 21 A and 21 B, a gate insulating layer 30 based on an insulating material such as silicon nitride is deposited onto the insulating substrate 10 such that it covers the gate line assembly and the storage capacitor electrode lines 27. Subsequently, an amorphous silicon layer 40 and a conductive type impurities-doped amorphous silicon layer 50 are sequentially deposited onto the gate insulating layer 30.

Thereafter, the amorphous silicon layer 40, the impurities-doped amorphous silicon layer 50 and the gate insulating layer 30 are patterned through photolithography to thereby form first contact holes 32 exposing the storage capacitor electrode lines 27.

As shown in Figs. 22A and 22B, the amorphous silicon layer 40 and the impurities-doped amorphous silicon layer 50 are patterned through photolithography to thereby form a semiconductor pattern 42 and an ohmic contact pattern 52.

As shown in Fig. 23A and 23B, a metallic layer is deposited onto the entire surface of the substrate 10, and patterned through photolithography to thereby form a data liiJe assembly, and storage capacitor conductive patterns 67. The data line assembly includes data lines 62, data pads 64, source electrodes 65, and drain electrodes 66. The storage capacitor conductive patterns 67 are connected to the storage capacitor electrode lines 27 through the first contact holes 32.

The ohmic contact pattern 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to thereby separate it into a first portion

55 contacting the source electrode 65, and a second portion 56 contacting the drain electrode 66.

As shown in Figs. 24A and 24B, a passivation layer 70 is formed on the entire surface of the substrate 10 having the data line assembly, the storage capacitor conductive patterns 67 and the semiconductor pattern 42 with silicon nitride or silicon oxide. The passivation layer 70 and the gate

insulating layer 30 are patterned through photolithography to thereby form

second to fourth contact holes 72, 74 and 76. The second and the third

contact holes 72 and 74 are formed at the passivation layer 70 while exposing the drain electrodes 66, and the data pads 64. The fourth contact

holes 76 are formed at the passivation layer 70 and the gate insulating layer 30 while exposing the gate pads 24.

As shown in Figs. 18 and 19, a transparent conductive layer based

on ITO or IZO is deposited onto the entire surface of the substrate 10. The transparent conductive layer is patterned through photolithography to thereby form pixel electrodes 82, subsidiary data pads 84,

and subsidiary gate pads 86. The pixel electrodes 82 are connected to the drain electrodes 66 through the second contact holes 72. The subsidiary data and gate pads 84 and 86 are connected to the data and gate pads 64 and 24 through the third and the fourth contact holes 74 and 76.

In this preferred embodiment, the storage capacitor conductive patterns 67 are placed at the pixel regions between the neighboring gate

lines. Alternatively, the storage capacitor conductive patterns 67 may be formed at the periphery of the pixel regions while bearing a bar shape.

Fig. 25 is a plan view of a thin film transistor array panel according to

a sixth preferred embodiment of the present invention, and Fig. 26 is a cross

sectional view of the thin film transistor array panel taken along the XXVI- XXVI' line of Fig. 25.

In this preferred embodiment, the storage capacitor conductive

patterns 67 are placed at both peripheral sides of the pixel regions while bearing a bar shape. The storage capacitor conductive patterns 67 are connected to the storage capacitor electrode lines 27 through the first contact holes 32 formed at the gate insulating layer 30.

The storage capacitor electrode lines 27 form storage capacitors in association with the pixel electrodes 82 while interposing the gate insulating layer 30 and the passivation layer 70. Furthermore, the storage capacitor conductive patterns 67 form other storage capacitors in association with the pixel electrodes 82 while interposing the passivation layer 70.

With such a structure, the electrostatic capacitance of the storage capacitors becomes increased even with > the same overlapping area compared to the case where only the storage capacitor electrode lines 27 are overlapped with the pixel electrodes 82. Consequently, the aperture ratio with respect to the storage capacity becomes enhanced.

Furthermore, as the bar-shaped storage capacitor conductive patterns 67 are placed between the pixel electrodes 82 and the data lines 62, leakage of light between the pixel electrodes 82 and the data lines 62 can be prevented.

In the fifth and sixth preferred embodiments of the present invention, the storage capacitor line assembly is formed in a separate manner. Alternatively, parts of the gate lines may be utilized as the storage capacitor electrodes.

Fig. 27 is a plan view of a thin film transistor array panel according to a seventh preferred embodiment of the present invention, and Fig. 28 is a cross sectional view of the thin film transistor array panel taken along the XXVIII -XXVIII' line of Fig. 27. In this preferred embodiment, the pixel electrodes arranged at any one gate line are overlapped with parts of the previous gate line to form storage capacitors. That is, parts of the gate lines are used to form the desired storage capacitors without forming a storage capacitor line assembly in a separate manner.

As shown in Fig. 27, the pixel electrodes 82 at the nth gate line 22 (Gn) are overlapped with the (n-1)th gate line 22 (Gn-1 ) while being extended in its area.

The storage capacitor conductive patterns 67 are partially overlapped with the gate lines 22 while interposing the gate insulating layer 30. The storage capacitor conductive patterns 67 are placed at the same plane as the data line assembly. The fourth contact holes 78 exposing the storage capacitor conductive patterns 67 are formed at the passivation layer 70. The storage capacitor conductive patterns 67 placed over the (n-1)th gate line 22 (Gn-1) are connected to the pixel electrodes 82 at the nth gate line 22 (Gn).

The storage capacitor conductive patterns 67 are overlapped with the gate lines 22 while interposing the gate insulating layer 30 to thereby form storage capacitors. The storage capacitor conductive patterns 68 placed over the (n-1)th gate line 22 (Gn-1) receive the relevant signals from the pixel electrodes 82 at the nth gate line 22 (Gn).

In the above structure, the storage capacity becomes significantly increased compared to the case where the storage capacitors are formed only through overlapping the pixel electrodes 82 with the gate lines 22. Furthermore, as a separate storage capacitor line assembly is not needed, the aperture ratio can be further enhanced.

The inventive structure may be well adapted for use with all of the liquid crystal display modes. Particularly, in case such a structure is employed for use with the optically compensated birefringence (OCB) mode, various advantages are resulted.

As the Δ ε value of the liquid crystal is great with the OCB mode

liquid crystal display, the difference between the dielectric constant at the initial state and the dielectric constant at the succeeding state as a function of the gray values is also great, and therefore, variation in the liquid crystal voltage is inevitably made to a large scale.

Meanwhile, as shown in Fig. 29, the waveform (time-brightness) curve of the response speed measured with all of the liquid crystal display modes bears a two-stepped waveform exhibiting two stepped differences.

As the response speed is measured while altering the total brightness from 10% to 90%, it turns out to be slower in case the brightness at the two-stepped portion is less than 90%.

The OCB mode liquid crystal display exhibits a characteristic in that the two-stepped waveform occurs at the first frame, and a normal brightness is maintained at the second frame or the third frame. Therefore, in case the electrostatic capacitance at the two-stepped portion is increased to be 90% or more, particularly 95% or more, the desired normal brightness can be maintained at the first frame, thereby making rapid response speed.

Table 1 lists the brightness values at the two-stepped portion over the waveform (time-brightness) curve of the response speed as a function of the ratio of the electrostatic capacitance Cst of the storage capacitors to the electrostatic capacitance Clc of the liquid crystal in the OCB mode liquid crystal display. Table 1

Figure imgf000043_0001

It can be known from Table 1 that as the storage capacity Cst is increased, the brightness at the two-stepped portion is approximated to 90%. Therefore, the rapid response speed can be obtained through increasing the storage capacity such that the brightness at the two-stepped portion goes over 90%. Particularly, in case the storage capacity is increased such that the brightness at the two-stepped portion goes over 95%, the response speed can be further enhanced. In order to increase the storage capacity to such a degree, the storage capacitors according to the first to seventh preferred embodiments may be applied for use in the OCB mode liquid crystal display. That is, the storage capacitor electrode lines are formed at the same plane as the data line assembly such that they are overlapped with the pixel electrodes while interposing only the passivation layer. In this structure, the storage capacity as well as the aperture ratio are significantly enhanced without enlarging the area of the storage capacitor electrode lines, compared to the case where the storage capacitor electrode lines are formed at the same plane as the gate line assembly such that they are overlapped with the pixel electrodes while interposing the passivation layer and the gate insulating layer. As only one of the passivation layer and the gate insulating layer is disposed between the storage capacitor electrodes, it is not needed to enlarge the area of the storage capacitor electrode components. Consequently, the storage capacity can be increased without decreasing the aperture ratio.

As described above, with the inventive structure, the storage capacity can be increased without decreasing the aperture ratio while enhancing the response speed. While the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and substitutions can be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

WHAT IS CLAIMED IS:
1 . A thin film transistor array panel comprising:
an insulating substrate;
a gate line assembly formed on the insulating substrate with gate
lines, and gate electrodes; a gate insulating layer covering the gate line assembly;
a semiconductor pattern formed on the gate insulating layer; a data line assembly formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing
over the gate lines, source electrodes connected to the data lines, and drain electrodes facing the source electrodes; storage capacitor electrode lines formed between the neighboring data lines while crossing over the gate lines; a passivation layer covering the data line assembly, the storage capacitor electrode lines and the semiconductor pattern while bearing contact holes exposing the drain electrodes; and pixel electrodes formed on the passivation layer while being
connected to the drain electrodes through the contact holes, the pixel electrodes being overlapped with the storage capacitor electrode lines.
2. The thin film transistor array panel of claim 1 further
comprising a common interconnection line commonly interconnecting the
storage capacitor electrode lines.
3. The thin film transistor array panel of claim 2 wherein the
common interconnection line is formed with the same material as the pixel
electrodes while crossing over the data lines in an insulated manner.
4. The thin film transistor array panel of claim 2 wherein the common interconnection line is formed with the same material as the gate lines while crossing over the data lines in an insulated manner.
5. The thin film transistor array panel of claim 3 wherein the passivation layer has a plurality of contact holes exposing the storage capacitor electrode lines, and the common interconnection line is connected to the storage capacitor electrode lines through the contact holes.
6. The thin film transistor array panel of claim 2 further comprising a subsidiary interconnection line connected to the storage capacitor electrode lines.
7. The thin film transistor array panel of claim 6 wherein the storage capacitor electrode lines and the subsidiary interconnection line are formed with the same material.
8. The thin film transistor array panel of claim 1 further comprising:
gate pads formed at one-sided end portions of the gate lines; data pads formed at one-sided end portions of the data lines; first contact holes formed at the passivation layer and the gate insulating layer while exposing the gate pads;
second contact holes formed at the passivation layer while exposing
the data pads; and
subsidiary gate and data pads connected to the gate and the data pads through the first and the second contact holes.
9. A liquid crystal display comprising: the thin film transistor array panel of claim 1 ; a counter substrate facing the thin film transistor array panel; and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.
10. The liquid crystal display of claim 9 having storage capacitors with an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.
1 1. The liquid crystal display of claim 10 wherein the electrostatic capacitance of the storage capacitors is greater than the electrostatic capacitance of the liquid crystal layer by 95% or more.
12. The liquid crystal display of claim 9 wherein the thin film transistor array panel further comprises a common interconnection line commonly interconnecting the storage capacitor electrode lines.
13. The liquid crystal display of claim 12 wherein the common interconnection line is formed with the same material as the pixel electrodes while crossing over the data lines in an insulated manner.
1 4. The liquid crystal display of claim 13 wherein the passivation
layer has a plurality of contact holes exposing the storage capacitor electrode
lines, and the common interconnection line is connected to the storage
capacitor electrode lines through the contact holes.
1 5. The liquid crystal display of claim 12 wherein the thin film
transistor array panel further comprises a subsidiary interconnection line
connected to the storage capacitor electrode lines.
1 6. The liquid crystal display of claim 1 5 wherein the storage
capacitor electrode lines and the subsidiary interconnection line are formed
with the same material.
1 7. A thin film transistor array panel comprising:
an insulating substrate;
a gate line assembly and a storage capacitor line assembly formed
on the insulating substrate, the gate line assembly having gate lines and gate
electrodes;
a gate insulating layer covering the gate line assembly and the
storage capacitor line assembly;
a semiconductor pattern formed on the gate insulating layer;
a data line assembly and storage capacitor conductive patterns
formed on the gate insulating layer overlaid with the semiconductor pattern,
the data line assembly having data lines, source electrodes and drain
electrodes, the storage capacitor conductive patterns being partially
overlapped with the storage capacitor line assembly to thereby form first
storage capacitors;
a passivation layer covering the data line assembly, the storage
capacitor conductive patterns and the semiconductor pattern;
first and second contact holes formed at the passivation layer while
exposing the drain electrodes and the storage capacitor conductive patterns,
respectively; and
pixel electrodes formed on the passivation layer while being
connected to the drain electrodes and the storage capacitor conductive
patterns through the first and the second contact holes, the pixel electrodes
forming second storage capacitors in association with parts of the storage
capacitor line assembly.
18. The thin film transistor array panel of claim 17 wherein the storage capacitor line assembly has storage capacitor electrode lines proceeding parallel to the gate lines, and storage capacitor electrode patterns connected to the storage capacitor electrode lines.
19. The thin film transistor array panel of claim 18 wherein the storage capacitor electrode patterns are overlapped with the storage capacitor conductive patterns to thereby form the first storage capacitors, and the storage capacitor electrode lines are overlapped with the pixel electrodes to thereby form the second storage capacitors.
20. The thin film transistor array panel of claim 19 wherein the storage capacitor electrode patterns are formed within pixel regions defined by the gate lines and the data lines.
21. The thin film transistor array panel of claim 19 wherein the storage capacitor electrode patterns are formed with a bar shape along the data lines while being overlapped with peripheral portions of the pixel electrodes.
22. A liquid crystal display comprising: the thin film transistor array panel of claim 17; a counter substrate facing the thin film transistor array panel; and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.
23. The liquid crystal display of claim 22 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.
24. A thin film transistor array panel comprising: an insulating substrate; a gate line assembly formed on the insulating substrate, the gate line
assembly having first gate lines, gate electrodes connected to the first gate
lines, and second gate lines spaced apart from the first gate lines with a
predetermined distance;
a gate insulating layer covering the gate line assembly;
a semiconductor pattern formed on the gate insulating layer while being overlapped with the gate electrodes;
a data line assembly and storage capacitor conductive patterns formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, the storage capacitor conductive patterns being partially overlapped with the second gate lines to thereby form first storage capacitors; a passivation layer covering the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern; first and second contact holes formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns, respectively; and
pixel electrodes formed at the passivation layer while being
connected to the drain electrodes and the storage capacitor conductive
patterns through the first and the second contact holes, the pixel electrodes
being partially overlapped with the second gate lines to thereby form second
storage capacitors.
25. A liquid crystal display comprising:
the thin film transistor array panel of claim 24; a counter substrate facing the thin film transistor array panel; and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.
26. The liquid crystal display of claim 25 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.
27. A thin film transistor array panel comprising: an insulating substrate; a gate line assembly and storage capacitor electrode lines formed on the insulating substrate, the gate line assembly having gate lines and gate electrodes; a gate insulating layer covering the gate line assembly and the storage capacitor electrode lines; first contact holes formed at the gate insulating layer while exposing the storage capacitor electrode lines; a semiconductor pattern formed on the gate insulating layer while
being overlapped with the gate electrodes; a data line assembly and storage capacitor conductive patterns
formed on the gate insulating layer overlaid with the semiconductor pattern,
the data line assembly having data lines, source electrodes and drain
electrodes, the storage capacitor conductive patterns being connected to the
storage capacitor electrode lines through the first contact holes;
a passivation layer covering the data line assembly, the storage
capacitor conductive patterns and the semiconductor pattern;
second contact holes formed at the passivation layer while exposing the drain electrodes; and pixel electrodes formed at the passivation layer while being connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the storage capacitor electrode lines to thereby form second storage capacitors.
28. The thin film transistor array panel of claim 27 wherein the storage capacitor electrode lines proceed parallel to the gate lines.
29. The thin film transistor array panel of claim 27 wherein the storage capacitor conductive patterns are overlapped with the storage capacitor electrode lines.
30. The thin film transistor array panel of claim 29 wherein the storage capacitor conductive patterns are formed within pixel regions defined by the gate lines and the data lines.
31 . The thin film transistor array panel of claim 27 wherein the storage capacitor electrode patterns are formed with a bar shape along the
data lines while being overlapped with peripheral portions of the pixel
electrodes.
32. A liquid crystal display comprising:
the thin film transistor array panel of claim 27;
a counter substrate facing the thin film transistor array panel; and
a liquid crystal layer sandwiched between the thin film transistor
array panel and the counter panel.
33. The liquid crystal display of claim 32 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the
electrostatic capacitance of the liquid crystal layer by 90% or more.
34. A thin film transistor array panel comprising:
an insulating substrate;
a gate line assembly formed on the insulating substrate, the gate line
assembly having first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance;
a gate insulating layer covering the gate line assembly; first contact holes formed at the gate insulating layer while partially exposing the second gate lines; a semiconductor pattern formed on the gate insulating layer while being overlapped with the gate electrodes; a data line assembly and storage capacitor conductive patterns formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing over the first and the
second gate lines, source electrodes and drain electrodes, the storage capacitor conductive patterns being connected to the second gate lines
through the first contact holes; a passivation layer covering the data line assembly, the storage
capacitor conductive patterns and the semiconductor pattern;
second contact holes formed at the passivation layer while exposing
the drain electrodes; and
pixel electrodes formed at the passivation layer while being
connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the second gate lines to thereby form second storage capacitors.
35. A liquid crystal display comprising: the thin film transistor array panel of claim 34; a counter substrate facing the thin film transistor array panel; and a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.
36. The liquid crystal display of claim 35 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.
37. A method of fabricating a thin film transistor array panel, the method comprising the steps of:
forming a gate line assembly and a storage capacitor line assembly on an insulating substrate such that the gate line assembly has gate lines and gate electrodes; forming a gate insulating layer such that the gate insulating layer
covers the gate line assembly and the storage capacitor line assembly; forming a semiconductor pattern on the gate insulating layer;
forming a data line assembly and storage capacitor conductive
patterns on the gate insulating layer overlaid with the semiconductor pattern
such that the data line assembly has data lines, source electrodes and drain
electrodes, and the storage capacitor conductive patterns are partially
overlapped with the storage capacitor line assembly to thereby form first
storage capacitors; forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern; forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive patterns, respectively; and forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes while forming second storage capacitors in association with parts of the storage capacitor lines assembly.
38. The method of claim 37 wherein the storage capacitor line assembly has storage capacitor electrode lines proceeding parallel to the gate lines, and storage capacitor electrode patterns connected to the storage capacitor electrode lines.
39. A method of fabricating a thin film transistor array panel, the method comprising the steps of: forming a gate line assembly on an insulating substrate such that the gate line assembly has first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance while proceeding parallel to the first gate lines; forming a gate insulating layer such that the gate insulating layer covers the gate line assembly; forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrodes; forming a data line assembly and storage capacitor conductive patterns on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are partially overlapped with the second gate lines to thereby form first storage capacitors; forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern; forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive patterns, respectively; and forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes while forming second storage capacitors in association with parts of the second gate lines.
40. A method of fabricating a thin film transistor array panel, the method comprising the steps of: forming a gate line assembly and storage capacitor electrode lines
on an insulating substrate such that the gate line assembly has gate lines and gate electrodes; forming a gate insulating layer such that the gate insulating layer covers the gate line assembly and the storage capacitor electrode lines; forming fir st contact holes at the gate insulating layer such that the first contact holes expose the storage capacitor electrode lines;
forming a semiconductor pattern on the gate insulating layer such
that the semiconductor pattern is overlapped with the gate electrodes;
- forming a data line assembly and storage capacitor conductive
patterns on the gate insulating layer overlaid with the semiconductor pattern
such that the data line assembly has data lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are connected to
the storage capacitor electrode lines through the first contact holes; forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;
forming second contact holes at the passivation layer such that the second contact holes expose the drain electrodes; and forming pixel electrodes on the passivation layer such that the pixel
electrodes are connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the storage capacitor electrode lines to thereby form
second storage capacitors.
41 . A method of fabricating a thin film transistor array panel, the
method comprising the steps of:
forming a gate line assembly on an insulating substrate such that the
gate line assembly has first gate lines, gate electrodes connected to the first
gate lines, and second gate lines spaced apart from the first gate lines with a
predetermined distance while proceeding parallel to the first gate lines; forming a gate insulating layer such that the gate insulating layer covers the gate line assembly; forming first contact holes at the gate insulating layer such that the first contact holes partially expose the second gate lines; forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrodes; forming a data line assembly and storage capacitor conductive patterns on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are connected to the second gate lines through the first contact holes; forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern; forming second contact holes at the passivation layer such that the second contact holes expose the drain electrodes; and forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the second gate lines to thereby form second storage capacitors.
PCT/KR2002/000334 2001-09-26 2002-02-27 Thin film transistor array panel for liquid crystal display and method for manufacturing the same WO2003036374A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR2001/59637 2001-09-26
KR1020010059637A KR20030026588A (en) 2001-09-26 2001-09-26 Thin film transistor plate and liquid crystal display
KR1020010077838A KR100840318B1 (en) 2001-12-10 2001-12-10 Thin film transistor substrate, fabricating method thereof and liquid crystal display
KR2001/77838 2001-12-10

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2003538809A JP2005506575A (en) 2001-09-26 2002-02-27 Thin film transistor substrate and a method of manufacturing a liquid crystal display device
US10/432,833 US7209192B2 (en) 2001-09-26 2002-02-27 Thin film transistor array panel for liquid crystal display and method for manufacturing the same
US11/697,174 US20070176178A1 (en) 2001-09-26 2007-04-05 Thin Film Transistor Array Panel for Liquid Crystal Display and Method for Manufacturing the Same
US11/697,122 US7990484B2 (en) 2001-09-26 2007-04-05 Thin film transistor array panel for liquid crystal display and method for manufacturing the same
US11/697,083 US8040446B2 (en) 2001-09-26 2007-04-05 Thin film transistor array panel for liquid crystal display and method for manufacturing the same

Related Child Applications (3)

Application Number Title Priority Date Filing Date
US11/697,174 Division US20070176178A1 (en) 2001-09-26 2007-04-05 Thin Film Transistor Array Panel for Liquid Crystal Display and Method for Manufacturing the Same
US11/697,083 Continuation US8040446B2 (en) 2001-09-26 2007-04-05 Thin film transistor array panel for liquid crystal display and method for manufacturing the same
US11/697,122 Division US7990484B2 (en) 2001-09-26 2007-04-05 Thin film transistor array panel for liquid crystal display and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2003036374A1 true WO2003036374A1 (en) 2003-05-01

Family

ID=26639365

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2002/000334 WO2003036374A1 (en) 2001-09-26 2002-02-27 Thin film transistor array panel for liquid crystal display and method for manufacturing the same

Country Status (5)

Country Link
US (4) US7209192B2 (en)
JP (3) JP2005506575A (en)
CN (1) CN1325984C (en)
TW (1) TW594120B (en)
WO (1) WO2003036374A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132689B2 (en) * 2003-04-03 2006-11-07 Lg.Philips Lcd Co., Ltd Liquid crystal display of horizontal electric field applying type and fabricating method thereof
US7602452B2 (en) 2005-09-13 2009-10-13 Epson Imaging Devices Corp. Liquid crystal display device and method for manufacturing the same
US7619695B2 (en) 2006-05-10 2009-11-17 Epson Imaging Devices Corporation Liquid crystal display and manufacturing method therefor
EP2360518A1 (en) * 2008-12-09 2011-08-24 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver
US8072570B2 (en) 2008-08-13 2011-12-06 Chunghwa Picture Tubes, Ltd. Liquid crystal display panel
USRE44181E1 (en) 2005-09-15 2013-04-30 Samsung Display Co., Ltd. Liquid crystal display having a reduced number of data driving circuit chips
US9196633B2 (en) 2008-09-19 2015-11-24 Semiconductor Energy Laboratory Co., Ltd. Display device

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101034744B1 (en) * 2004-06-25 2011-05-17 엘지디스플레이 주식회사 thin film transistor structure of liquid crystal display device
KR101061856B1 (en) 2004-11-03 2011-09-02 삼성전자주식회사 Thin film transistor array panel
US7586121B2 (en) 2004-12-07 2009-09-08 Au Optronics Corp. Electroluminescence device having stacked capacitors
KR101122231B1 (en) 2004-12-17 2012-03-19 삼성전자주식회사 Thin film transistor array panel using organic semiconductor and manufacturing method thereof
KR20060070349A (en) * 2004-12-20 2006-06-23 삼성전자주식회사 Thin film transistor array panel and method for manufacturing the same
KR101246023B1 (en) 2005-01-06 2013-03-26 삼성디스플레이 주식회사 Array substrate and display apparatus having the same
KR101112549B1 (en) * 2005-01-31 2012-06-12 삼성전자주식회사 Thin film transistor array panel
KR20060098522A (en) * 2005-03-03 2006-09-19 삼성전자주식회사 Organic thin film transistor array panel and method for manufacturing the same
CN100454117C (en) 2005-06-08 2009-01-21 友达光电股份有限公司 Picture element structure suitable for wide-angle liquid crystal display and manufacturing method
CN100485470C (en) 2005-09-13 2009-05-06 爱普生映像元器件有限公司 Liquid crystal display device and method for manufacturing the same
JP4900332B2 (en) * 2005-09-13 2012-03-21 ソニー株式会社 Manufacturing method of liquid crystal display device
KR101205766B1 (en) * 2005-12-30 2012-11-28 엘지디스플레이 주식회사 Liquid crystal display device
KR101184068B1 (en) 2005-12-30 2012-09-19 엘지디스플레이 주식회사 Array substrate for liquid crystal display and method for manufacturing the same
KR101204365B1 (en) 2006-01-16 2012-11-26 삼성디스플레이 주식회사 Liquid crystal display panel and method of manufacturing the same
KR101257380B1 (en) * 2006-04-04 2013-04-23 삼성디스플레이 주식회사 Display Apparatus
KR101306206B1 (en) * 2006-04-24 2013-09-10 삼성디스플레이 주식회사 Array substrate, display panel having the same and method for making the same
KR101238337B1 (en) * 2006-05-12 2013-03-04 삼성디스플레이 주식회사 Array subatrate and liquid crystal display device having the same
KR101407285B1 (en) * 2006-05-22 2014-06-13 엘지디스플레이 주식회사 Liquid Crystal Display Device and Method for Driving the Same
JP4211855B2 (en) 2006-05-29 2009-01-21 エプソンイメージングデバイス株式会社 Liquid crystal display device and manufacturing method thereof
CN100529852C (en) * 2006-06-09 2009-08-19 群康科技(深圳)有限公司;群创光电股份有限公司 Liquid crystal display panel
US20100309420A1 (en) * 2006-06-15 2010-12-09 Mikuni Electoron Co. Ltd. Low-cost large-screen wide-angle fast-response liquid crystal display apparatus
JP5477523B2 (en) 2006-06-15 2014-04-23 三国電子有限会社 Low cost large screen wide viewing angle fast response liquid crystal display
KR20080000202A (en) 2006-06-27 2008-01-02 삼성전자주식회사 Display substrate and display panel having the same
US8330883B2 (en) 2006-07-19 2012-12-11 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, display, television receiver
KR20080009889A (en) * 2006-07-25 2008-01-30 삼성전자주식회사 Liquid crystal display
JP5727120B2 (en) * 2006-08-25 2015-06-03 三星ディスプレイ株式會社Samsung Display Co.,Ltd. Liquid crystal display
KR101349092B1 (en) * 2006-09-07 2014-01-09 삼성디스플레이 주식회사 Array substrate and display apparatus having the same
CN101140938B (en) 2006-09-07 2010-05-12 中华映管股份有限公司 Thin-film transistor array substrates and method of producing the same
CN100557806C (en) * 2006-09-11 2009-11-04 中华映管股份有限公司 The pixel structure
KR101309552B1 (en) * 2006-11-01 2013-09-23 삼성디스플레이 주식회사 Array substrate and display panel having the same
TWI349915B (en) * 2006-11-17 2011-10-01 Chunghwa Picture Tubes Ltd Pixel structure and repair method thereof
KR101370969B1 (en) * 2006-11-30 2014-03-10 엘지디스플레이 주식회사 Photocurable organic material
JP4569836B2 (en) 2007-02-23 2010-10-27 ソニー株式会社 Liquid crystal device
JP2008216435A (en) * 2007-03-01 2008-09-18 Seiko Epson Corp Liquid crystal device and electronic equipment
JP4586811B2 (en) * 2007-03-09 2010-11-24 エプソンイメージングデバイス株式会社 Electro-optical device and substrate for electro-optical device
US7751001B2 (en) * 2007-03-21 2010-07-06 Chimel Innolux Corporation Transflective LCD with reflective layer connected to reference voltage greater than 0.5 Vrms and less than LC threshold voltage
CN100587573C (en) 2007-08-17 2010-02-03 北京京东方光电科技有限公司 TFT-LCD array substrate structure and manufacturing method thereof
CN100536145C (en) 2007-10-12 2009-09-02 友达光电股份有限公司 Pixel array structure and manufacturing method therefor
TWI356940B (en) * 2007-10-24 2012-01-21 Chunghwa Picture Tubes Ltd Liquid crystal display panel
JP5292066B2 (en) 2007-12-05 2013-09-18 株式会社半導体エネルギー研究所 Display device
KR20090126766A (en) * 2008-06-05 2009-12-09 삼성전자주식회사 Thin film transistor panel
US8547492B2 (en) 2009-02-03 2013-10-01 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit and television receiver
WO2010089820A1 (en) * 2009-02-03 2010-08-12 シャープ株式会社 Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device and television receiver
US8952949B2 (en) * 2009-06-19 2015-02-10 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver
EP2495717A1 (en) * 2009-10-28 2012-09-05 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver
KR20110089915A (en) 2010-02-02 2011-08-10 삼성전자주식회사 Display substrate, method of manufacturing the same, and display panel
CN102280443B (en) * 2010-06-08 2014-06-11 北京京东方光电科技有限公司 Structure of array substrate and manufacturing method thereof
KR20120012741A (en) * 2010-08-03 2012-02-10 엘지디스플레이 주식회사 Liquid crystal display device
TW201215979A (en) * 2010-10-15 2012-04-16 Chunghwa Picture Tubes Ltd Liquid crystal display
CN102243406B (en) * 2011-07-06 2013-05-01 南京中电熊猫液晶显示科技有限公司 Self-compensated storage capacitor pixel structure for improving variation of tone curve
JP5674587B2 (en) 2011-08-05 2015-02-25 株式会社ジャパンディスプレイ Liquid crystal display
CN102569190B (en) * 2012-02-10 2014-02-05 福建华映显示科技有限公司 Pixel structure and manufacturing method thereof
CN103676369A (en) * 2012-09-13 2014-03-26 北京京东方光电科技有限公司 Array substrate, array substrate manufacturing method and display device
CN103779362B (en) * 2012-10-17 2016-04-27 上海天马微电子有限公司 The manufacture method of the dull and stereotyped sniffer of X ray

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950029822A (en) * 1994-04-12 1995-11-24 김광호 A liquid crystal display device
KR960002917A (en) * 1994-06-22 1996-01-26 김광호 A liquid crystal display device and a manufacturing method for improving the aperture ratio
KR970007427A (en) * 1995-07-24 1997-02-21 김광호 The pixel circuit of a thin film transistor liquid crystal display device

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2589820B2 (en) 1989-08-14 1997-03-12 シャープ株式会社 Active matrix display device
JPH03163529A (en) 1989-11-22 1991-07-15 Sharp Corp Active matrix display device
JPH03294824A (en) 1990-04-13 1991-12-26 Nec Corp Active matrix type liquid crystal display element array
JPH04326329A (en) 1991-04-26 1992-11-16 Sharp Corp Liquid crystal display device and its manufacture
JP2827570B2 (en) * 1991-05-14 1998-11-25 三菱電機株式会社 Liquid crystal display
JP3059783B2 (en) 1991-07-29 2000-07-04 三洋電機株式会社 The liquid crystal display device
JPH06148681A (en) 1992-11-10 1994-05-27 Sanyo Electric Co Ltd Liquid crystal display device
JPH08306926A (en) * 1995-05-07 1996-11-22 Semiconductor Energy Lab Co Ltd Liquid crystal electrooptical system
JP3143042B2 (en) 1995-05-31 2001-03-07 カシオ計算機株式会社 The liquid crystal display element
JPH0926564A (en) * 1995-07-10 1997-01-28 Matsushita Electric Ind Co Ltd Liquid crystal display device
US5835177A (en) * 1995-10-05 1998-11-10 Kabushiki Kaisha Toshiba Array substrate with bus lines takeout/terminal sections having multiple conductive layers
JP3287985B2 (en) * 1995-10-30 2002-06-04 シャープ株式会社 A liquid crystal panel and defect correction method thereof
KR100229677B1 (en) 1996-06-14 1999-11-15 구자홍 Storage capacitor and its manufacturing method of liquid crystal display device
KR100219119B1 (en) 1996-08-31 1999-09-01 구자홍 Common line contacting part and its forming method of liquid crystal display device
CN1148600C (en) * 1996-11-26 2004-05-05 三星电子株式会社 Thin film transistor substrate and manufacturing methods thereof
KR100229613B1 (en) * 1996-12-30 1999-11-15 구자홍 Lcd device and its manufacturing method
JPH10213812A (en) * 1997-01-31 1998-08-11 Sharp Corp Active matrix type liquid crystal display device
JPH10239699A (en) 1997-02-25 1998-09-11 Advanced Display:Kk Liquid crystal display device
JPH10339885A (en) * 1997-06-09 1998-12-22 Hitachi Device Eng Co Ltd Active matrix type liquid crystal display device
KR100265573B1 (en) 1997-06-25 2000-09-15 김영환 Super high aperture lcd and method for fabricating the same
KR100262404B1 (en) 1997-06-26 2000-08-01 김영환 Super high aperture lcd and method for fabricating the same
US6335770B1 (en) * 1997-07-22 2002-01-01 Lg. Philips Lcd Co., Ltd. In-plane switching mode LCD with specific arrangement of common bus line, data electrode, and common electrode
KR100271037B1 (en) * 1997-09-05 2000-11-01 구본준, 론 위라하디락사 Structure and fabrication method of lcd
KR100502093B1 (en) 1997-09-25 2005-07-08 삼성전자주식회사 A liquid crystal display device and a manufacturing method using an organic insulating layer
JPH11271791A (en) * 1998-03-26 1999-10-08 Toshiba Corp Liquid crystal display device
TW413844B (en) 1998-11-26 2000-12-01 Samsung Electronics Co Ltd Manufacturing methods of thin film transistor array panels for liquid crystal displays and photolithography method of thin films
JP3134866B2 (en) * 1999-02-05 2001-02-13 日本電気株式会社 The liquid crystal display device and a method of manufacturing the same
KR100303069B1 (en) 1999-06-03 2001-10-29 구본준, 론 위라하디락사 LCD device and the same method
KR100543042B1 (en) 1999-06-03 2006-01-20 삼성전자주식회사 a manufacturing method of a thin film transistor panel for liquid crystal displays
JP3844913B2 (en) * 1999-06-28 2006-11-15 アルプス電気株式会社 Active matrix type liquid crystal display device
KR100507271B1 (en) * 1999-06-30 2005-08-10 비오이 하이디스 테크놀로지 주식회사 LCD having high aperture ratio and high transmittance and method for manufacturing the same
JP3464944B2 (en) * 1999-07-02 2003-11-10 シャープ株式会社 A thin film transistor substrate, its manufacturing method and a liquid crystal display device
TW478014B (en) 1999-08-31 2002-03-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing thereof
KR100348995B1 (en) 1999-09-08 2002-08-17 엘지.필립스 엘시디 주식회사 The method for fabricating liquid crystal display using four masks and the liquid crystal display thereof
JP4700156B2 (en) 1999-09-27 2011-06-15 株式会社半導体エネルギー研究所 Semiconductor device
EP1174758A4 (en) 1999-12-03 2007-07-18 Mitsubishi Electric Corp Liquid crystal display
JP2001255549A (en) * 2000-03-09 2001-09-21 Matsushita Electric Ind Co Ltd Liquid crystal display device
KR100726132B1 (en) * 2000-10-31 2007-06-12 엘지.필립스 엘시디 주식회사 A method for fabricating array substrate for liquid crystal display device and the same
KR100392850B1 (en) * 2000-12-29 2003-07-28 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Device and Fabricating Method Thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950029822A (en) * 1994-04-12 1995-11-24 김광호 A liquid crystal display device
KR960002917A (en) * 1994-06-22 1996-01-26 김광호 A liquid crystal display device and a manufacturing method for improving the aperture ratio
KR970007427A (en) * 1995-07-24 1997-02-21 김광호 The pixel circuit of a thin film transistor liquid crystal display device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132689B2 (en) * 2003-04-03 2006-11-07 Lg.Philips Lcd Co., Ltd Liquid crystal display of horizontal electric field applying type and fabricating method thereof
US7553708B2 (en) * 2003-04-03 2009-06-30 Lg Display Co., Ltd. Fabricating method for a liquid crystal display of horizontal electric field applying type
US7602452B2 (en) 2005-09-13 2009-10-13 Epson Imaging Devices Corp. Liquid crystal display device and method for manufacturing the same
USRE46035E1 (en) 2005-09-15 2016-06-21 Samsung Display Co., Ltd. Liquid crystal display having a reduced number of data driving circuit chips
USRE45187E1 (en) 2005-09-15 2014-10-14 Samsung Display Co., Ltd. Liquid crystal display having a reduced number of data driving circuit chips
USRE44181E1 (en) 2005-09-15 2013-04-30 Samsung Display Co., Ltd. Liquid crystal display having a reduced number of data driving circuit chips
USRE47431E1 (en) 2005-09-15 2019-06-11 Samsung Display Co., Ltd. Liquid crystal display having a reduced number of data driving circuit chips
US7619695B2 (en) 2006-05-10 2009-11-17 Epson Imaging Devices Corporation Liquid crystal display and manufacturing method therefor
US8072570B2 (en) 2008-08-13 2011-12-06 Chunghwa Picture Tubes, Ltd. Liquid crystal display panel
US9196633B2 (en) 2008-09-19 2015-11-24 Semiconductor Energy Laboratory Co., Ltd. Display device
US8531620B2 (en) 2008-12-09 2013-09-10 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver
EP2360518A1 (en) * 2008-12-09 2011-08-24 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver
EP2360518A4 (en) * 2008-12-09 2012-07-04 Sharp Kk Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver

Also Published As

Publication number Publication date
JP2009145908A (en) 2009-07-02
JP2005506575A (en) 2005-03-03
US7209192B2 (en) 2007-04-24
US8040446B2 (en) 2011-10-18
US20040114059A1 (en) 2004-06-17
CN1488083A (en) 2004-04-07
US20070188669A1 (en) 2007-08-16
CN1325984C (en) 2007-07-11
US7868953B2 (en) 2011-01-11
US20070176178A1 (en) 2007-08-02
TW594120B (en) 2004-06-21
JP2012113327A (en) 2012-06-14
US20070195569A1 (en) 2007-08-23

Similar Documents

Publication Publication Date Title
US7259820B2 (en) Active matrix type liquid crystal display device and method of manufacturing the same
US6999134B2 (en) Liquid crystal display and thin film transistor array panel therefor
CN100435012C (en) Liquid crystal display device and fabrication method thereof
JP4570278B2 (en) Active matrix substrate
US5771083A (en) Active matrix substrate and liquid crystal display device
US7499114B2 (en) Liquid crystal display device having touch screen function and method of fabricating the same
US8411244B2 (en) Liquid crystal display device and fabricating method thereof with a simplified mask process
US6087678A (en) Thin-film transistor display devices having composite electrodes
US6936845B2 (en) Thin film transistor panel for liquid crystal display
US6862052B2 (en) Liquid crystal display, thin film transistor array panel for liquid crystal display and manufacturing method thereof
KR100259909B1 (en) Tft-array and manufacturing method thereof
US7102168B2 (en) Thin film transistor array panel for display and manufacturing method thereof
US8619207B2 (en) Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same
US5923390A (en) Liquid crystal display with high aperture ratio and method for manufacturing the same
US6671010B2 (en) Array substrate for LCD device and method of fabricating the same
US7632723B2 (en) Thin film transistor array panel and manufacturing method thereof
US9134583B2 (en) Array substrate for liquid crystal display device, liquid crystal display device and method of fabricating the same
US7202498B2 (en) Liquid crystal display, thin film transistor array panel therefor, and manufacturing method thereof
CN1325984C (en) Thin film transistor array substrate of liquid crystal display device and producing method thereof
US20040001170A1 (en) Liquid crystal display device having array substrate of color filter on thin film transistor structure and manufacturing method thereof
US20190212617A1 (en) Liquid crystal display and panel therefor
US7751021B2 (en) Liquid crystal display and fabricating method thereof
JP3654474B2 (en) Matrix array and a liquid crystal display device and manufacturing method thereof of an active matrix liquid crystal display device
US6738109B2 (en) Thin film transistor substrate for liquid crystal display panel and manufacturing method thereof
US7154569B2 (en) Liquid crystal display and thin film transistor array panel therefor

Legal Events

Date Code Title Description
AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 028040287

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 10432833

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2003538809

Country of ref document: JP

122 Ep: pct application non-entry in european phase