KR950021561A - Storage electrode formation method of DRAM cell - Google Patents

Storage electrode formation method of DRAM cell Download PDF

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Publication number
KR950021561A
KR950021561A KR1019930030485A KR930030485A KR950021561A KR 950021561 A KR950021561 A KR 950021561A KR 1019930030485 A KR1019930030485 A KR 1019930030485A KR 930030485 A KR930030485 A KR 930030485A KR 950021561 A KR950021561 A KR 950021561A
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KR
South Korea
Prior art keywords
layer
forming
storage electrode
doped
undoped
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KR1019930030485A
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Korean (ko)
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KR970011670B1 (en
Inventor
우상호
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김주용
현대전자산업 주식회사
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Priority to KR1019930030485A priority Critical patent/KR970011670B1/en
Publication of KR950021561A publication Critical patent/KR950021561A/en
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Publication of KR970011670B1 publication Critical patent/KR970011670B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 디램셀(DRAM cell)의 저장전극 형성방법에 관한 것으로, 저장전극 콘택을 형성하고 그 상부에 벨로우형 저장전극을 형성한 후, 열공정으로 그레인 바운더리(grain boundary)에만 불순물을 확산시켜 저장전극의 상부면을 반구형 다결정실리콘으로 형성하여 저장전극의 표면적을 극대화시키는 기술이다.The present invention relates to a method of forming a storage electrode of a DRAM cell, and after forming a storage electrode contact and forming a bellow type storage electrode thereon, by diffusing impurities only at grain boundaries in a thermal process. It is a technology to maximize the surface area of the storage electrode by forming the upper surface of the storage electrode made of hemispherical polycrystalline silicon.

Description

디램셀의 저장전극 형성방법Storage electrode formation method of DRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제5도는 본 발명의 실시예로 디램셀의 저장전극 형성공정을 도시한 단면도.1 to 5 are cross-sectional views showing a storage electrode forming process of a DRAM cell according to an embodiment of the present invention.

Claims (3)

일반적인 MOS구조에서 디램셀을 형성함에 있어서, 예정된 부위에 필드산화막, 활성영역, 워드라인, 소오스/드레인영역 및 비트라인을 형성시킨 후, 평탄화된 표면 상부에 전하저장전극이 형성될 부위에 저장전극 콘택홀을 형성하는 공정과, 도판트가 도핑되지 않은 비정질 실리콘막을 제1층, 도핑된 층을 제2층, 도핑되지 않은 층을 제3층, 도핑된 층을 제4층, 도핑되지 않은 층을 제5층으로 형성하는 공정과, 전체구조상부에 저장전극 마스크용 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 사용하여 하부층을 식각하여 패턴을 형성한 후, 상기 감광막패턴을 제거하는 공정과, 열공정을 실시하여 그레인 바운더리를 따라 불순물을 확산시키는 공정과, 불순물이 도핑된 다결정실리콘막을 습식식각용액으로 일정폭만큼 제거하여 다결정실리콘패턴을 형성하고 상부의 그레인 바운더리를 따라 식각되므로써 상부에 반구형 다결정실리콘층을 형성하는 공정을 포함하는 디램셀의 저장전극 형성방법.In forming a DRAM cell in a general MOS structure, after forming a field oxide film, an active region, a word line, a source / drain region and a bit line in a predetermined region, a storage electrode is formed in a region where a charge storage electrode is to be formed on the planarized surface. Forming a contact hole, a first layer of an undoped doped amorphous silicon film, a second layer of a doped layer, a third layer of an undoped layer, a fourth layer of a doped layer, an undoped layer Forming a fifth layer, forming a photoresist pattern for a storage electrode mask on the entire structure, forming a pattern by etching the lower layer using the photoresist pattern, and then removing the photoresist pattern; And diffusing the impurities along the grain boundaries by thermal processing, and removing the polycrystalline silicon pattern doped with a certain amount by a wet etching solution. Sex and D. The method for forming a storage electrode of raemsel comprising a step of forming a polysilicon layer on the semi-spherical doemeurosseo etching along the grain boundary of the upper. 제1항에 있어서, 상기 제5층의 다결정실리콘막은 다른층의 다결정실리콘막보다 두배 두껍게 증착하는 것을 특징으로 하는 디램셀의 저장전극 형성방법.The method of claim 1, wherein the polysilicon film of the fifth layer is deposited twice as thick as the polysilicon film of another layer. 제1항에 있어서, 상기 열공정은 650℃-700℃에서 30분 내지 1시간 정도 1차 열처리한 다음, 650℃에서 1시간 정도 2차 열처리하는 것을 특징으로 하는 디램셀의 저장전극 형성방법.2. The method of claim 1, wherein the thermal process is performed by heat treatment at 650 ° C.-700 ° C. for about 30 minutes to 1 hour and then second heat treatment at 650 ° C. for about 1 hour. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930030485A 1993-12-28 1993-12-28 A method for fabricating stack type dram cell KR970011670B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930030485A KR970011670B1 (en) 1993-12-28 1993-12-28 A method for fabricating stack type dram cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930030485A KR970011670B1 (en) 1993-12-28 1993-12-28 A method for fabricating stack type dram cell

Publications (2)

Publication Number Publication Date
KR950021561A true KR950021561A (en) 1995-07-26
KR970011670B1 KR970011670B1 (en) 1997-07-14

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Application Number Title Priority Date Filing Date
KR1019930030485A KR970011670B1 (en) 1993-12-28 1993-12-28 A method for fabricating stack type dram cell

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Publication number Publication date
KR970011670B1 (en) 1997-07-14

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