KR960026172A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR960026172A KR960026172A KR1019940035730A KR19940035730A KR960026172A KR 960026172 A KR960026172 A KR 960026172A KR 1019940035730 A KR1019940035730 A KR 1019940035730A KR 19940035730 A KR19940035730 A KR 19940035730A KR 960026172 A KR960026172 A KR 960026172A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- charge storage
- storage electrode
- semiconductor substrate
- junction layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 7
- 238000004519 manufacturing process Methods 0.000 title claims abstract 3
- 238000000034 method Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract 5
- 239000010410 layer Substances 0.000 claims abstract 4
- 238000005530 etching Methods 0.000 claims abstract 2
- 239000011229 interlayer Substances 0.000 claims abstract 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 소자가 형성될 예정된 지역의 반도체 기판을 전체두께중 일정두께 식각하는 단계; 상기 반도체 기판이 식각된 부위에 접합층을 구비하는 통상적인 트랜지스터 구조를 형성하는 단계; 전체구조 상부에 층간절연막을 형성하는 단계; 상기 트랜지스터의 접합층에 전하저장전극을 콘택시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법에 관한 것으로, 기판의 타포로지를 심화시키지 않는 상태에서 전하저장전극의 표면적을 크게함으로써 공정의 용이함을 가져오고 고집적 소자의 셀당 필요한 캐패시터 용량을 확보하여 소자의 특성을 향상시키는 효과를 가져온다.The present invention comprises the steps of etching the semiconductor substrate of the region where the device is to be formed a certain thickness of the total thickness; Forming a conventional transistor structure having a junction layer on a portion where the semiconductor substrate is etched; Forming an interlayer insulating film on the entire structure; A method of manufacturing a semiconductor device comprising contacting a charge storage electrode with a junction layer of the transistor, wherein the process area is increased by increasing the surface area of the charge storage electrode without deepening the substrate. Importing and securing the required capacitor capacity per cell of the high-density device has the effect of improving the characteristics of the device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1A도 내지 제1C도는 본 발명의 일실시예에 따른 전하저장전극 형성 공정 단면도.1A to 1C are cross-sectional views of a charge storage electrode forming process according to an embodiment of the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940035730A KR960026172A (en) | 1994-12-21 | 1994-12-21 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940035730A KR960026172A (en) | 1994-12-21 | 1994-12-21 | Semiconductor device manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960026172A true KR960026172A (en) | 1996-07-22 |
Family
ID=66688754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940035730A KR960026172A (en) | 1994-12-21 | 1994-12-21 | Semiconductor device manufacturing method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960026172A (en) |
-
1994
- 1994-12-21 KR KR1019940035730A patent/KR960026172A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |