KR950001999A - 칩-온-보드형 반도체 패키지 및 그 제조방법 - Google Patents

칩-온-보드형 반도체 패키지 및 그 제조방법 Download PDF

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Publication number
KR950001999A
KR950001999A KR1019930011671A KR930011671A KR950001999A KR 950001999 A KR950001999 A KR 950001999A KR 1019930011671 A KR1019930011671 A KR 1019930011671A KR 930011671 A KR930011671 A KR 930011671A KR 950001999 A KR950001999 A KR 950001999A
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South Korea
Prior art keywords
chip
dam
contact pads
resin layer
semiconductor package
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KR1019930011671A
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English (en)
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KR960000220B1 (ko
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권영신
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김광호
삼성전자 주식회사
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Publication of KR950001999A publication Critical patent/KR950001999A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

이 발명은 반도체 칩이 PCB상에 직접 실장되어 있는 COB형 반도체 패키지 및 그 제조방법에 관한 것으로서, 상기 PCB의 금속배선 형성시에 반도체 칩 및 접속패트들이 내부에 포함되도록 구리박막으로 댐을 형성하고, 상기 댐을 습식산화시켜 표면이 거친 산화구리로 된 댐을 형성한다. 그다음 상기 반도체 칩을 감싸 보호하는 수지층을 상기 댐과 접촉되도록 형성하여 상기 수지층의 테두리 부분의 접착력을 향상시켰다. 따라서 상기 COB형 반도체 패키지의 반도체 칩을 보호하는 수지층의 박리에 의한 불량을 방지하여 신뢰성을 향상시킬 수 있으며, 상기 댐이 PCB상에 금속 배선을 형성할 때 도시에 형성되므로 제조 공정이 간단하다.

Description

칩－옵 －보드형 반도체 패키지 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 이 발명에 따른 칩－온－보드형 반도체 패키지의 일 실시예의 평면도, 제5도는 제4도에서의 선 Ｖ－Ｖ에 따른 단면도, 제6도는 이 발명에 따른 칩－온－보드형 패키지의 다른 실시예의 평면도, 제7도는 제6도에서 선 Ⅶ－Ⅶ에 따른 단면도이다.

Claims (5)

  1. 금속배선 및 다이 어태치 패드가 형성되어 있는 인쇄회로기판과, 상기 인쇄회로기판 일측의 다이 어태치 패드상에 실장되어 있는 반도체 칩과, 상기 다이 어태치 패드들 주변의 인쇄회로기판상에 형성되어 있는 접촉패드들과, 상기 접촉패드들과 상기 반도체 칩의 본딩패드들을 연결하는 와이어들과, 상기 와이어와 반도체 칩 및 접촉패드들을 감싸 보호하는 수지층을 구비하는 칩－온－보드형 반도체 패키지에 있어서; 상기 접촉패드들을 내부에 포함하도록 표면이 거친 산화구리막으로 PCB상에 형성되어 있는 댐과; 상기 수지층의 테두리 부분이 상기 댐을 덮도록 형성되어 있는 상기 수지층과 산화구리막의 접착력에 의해 상기 수지층의 박리를 방지할 수 있는 칩－온－보드형 반도체 패키지.
  2. 제1항에 있어서, 상기 수지층이 신축성이 있는 실리콘 수지로 형성되어 있는 칩－온－보드형 반도체 패키지.
  3. 제1항 또는 제2항에 있어서, 상기 인쇄회로기판의 타측에 상기 접촉패드와 연결되는 별도의 접촉패드들을 구비하는 IC카드용으로 사용되는 칩－온－보드형 반도체 패키지.
  4. 인쇄회로기판상에 금속배선들과 접촉패드들을 형성하는 공정과, 상기 인쇄회로기판의 다이 어태치 패드상에 반도체 칩을 실장하는 공정과, 상기 반도체 칩의 본딩패드들과 상기 접촉패드들을 와이어로 연결하는 공정과, 상기 반도체 칩과 와이어 및 접촉패드들을 감싸 보호하는 수지층을 형성하는 공정을 구비하는 칩－온－보드형 반도체 패키지의 제조방법에 있어서; 상기 인쇄회로기판상에 접촉패드들을 형성하는 공정시, 상기 접촉패드들 및 반도체 칩을 내부에 포함하며, 상기 인쇄기판의 금속배선들과는 단락되어 있는 댐을 구리박막으로 형성하는 공정과; 상기 댐을 산화시켜 산화구리로 된 댐을 형성한 후, 상기 수지층이 댐을 덮도록 형성하는 공정을 구비하여 상기 수지층의 박리를 방지할 수 있는 칩－온－보드형 반도체 패키지의 제조방법.
  5. 제4항에 있어서, 상기 댐을 형성하는 산화구리층을 습식식각 방법으로 형성하는 칩－온－보드형 반도체 패키지의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930011671A 1993-06-25 1993-06-25 칩-온-보드형 반도체 패키지 및 그 제조 방법 KR960000220B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930011671A KR960000220B1 (ko) 1993-06-25 1993-06-25 칩-온-보드형 반도체 패키지 및 그 제조 방법

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Application Number Priority Date Filing Date Title
KR1019930011671A KR960000220B1 (ko) 1993-06-25 1993-06-25 칩-온-보드형 반도체 패키지 및 그 제조 방법

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KR950001999A true KR950001999A (ko) 1995-01-04
KR960000220B1 KR960000220B1 (ko) 1996-01-03

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