KR940022255A

KR940022255A - Inverter communication method with multiple processors

Info

Publication number: KR940022255A
Application number: KR1019930003659A
Authority: KR
Inventors: 강준구
Original assignee: 성기설; 금성계전 주식회사
Priority date: 1993-03-11
Filing date: 1993-03-11
Publication date: 1994-10-20

Abstract

본 발명은 복수 프로세서를 갖는 인버터 통신방법에 관한 것으로 종래의 복수 프로세서를 갖는 인버터 통신방법은 원하는 데이타를 선택하여 통신할 수 없기때문에 원하는 종류의 데이타를 출력하기 위해서는 순서가 정해진 모든 데이타가 통신된 후 통신순서가 될때까지 기다려야 하므로 통신이 지연되고, 또한 외부 노이즈의 영향으로 통신순서가 하나라도 변경되면, 그 후의 데이타는 전부 비정상적인 데이타값이 교환되는 문제점이 있었다.The present invention relates to an inverter communication method having a plurality of processors. In the conventional inverter communication method having a plurality of processors, since the desired data cannot be selected and communicated, in order to output a desired type of data, all ordered data are communicated. Since communication must be delayed until the communication order is reached, and if any communication order is changed due to the influence of external noise, there is a problem that all subsequent data are replaced with abnormal data values.

본 발명은 이러한 문제점을 해결하기 위하여 통신하고자 하는 데이타의 종류를 코드로서 지정하여 데이타를 변경코자 할시 통신준비신호를 제어하여 노이즈의 발생을 방지함으로써 비정상적인 데이타가 읽히는 것을 방지하여 통신시간의 지연 및 오동작을 방지하는 것이다.In order to solve this problem, the present invention designates the type of data to be communicated as a code and controls a communication ready signal when changing data to prevent the occurrence of noise, thereby preventing abnormal data from being read and delaying and malfunctioning of the communication time. To prevent.

Description

Inverter communication method with multiple processors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 복수 프로세서를 갖는 인버터 통신장치 구성도,1 is a block diagram of a conventional inverter communication apparatus having a plurality of processors,

제2도는 본 발명 복수 프로세서를 갖는 인버터 통신장치 구성도,2 is a block diagram of an inverter communication apparatus having a plurality of processors of the present invention;

제5도의 (가) 내지 (라)는 프로세서1(10)의 입출력 신호도,(A) to (D) of FIG. 5 shows an input / output signal of the processor 1 (10),

제6도의 (가) 내지 (라)는 프로세서2(20)의 입출력 신호도이다.6A to 6D are input / output signal diagrams of the processor 2 20.

Claims

A first step of determining whether the input communication ready signal 2 is "1"; if the communication ready signal 2 is "1", the data value is inputted with the communication ready signal 1 as "0", and the corresponding data value A second step of increasing the data code, a third step of changing the communication ready signal 1 to "1" after outputting the data code increased in the second step and corresponding data corresponding to the data code, and executing another program; Inverter communication method having a plurality of processors, characterized in that consisting of steps.

A first step of determining whether the inputted communication ready signal 1 is "1"; and if the communication ready signal 1 is "1" in the first step, the data code designated by the other party with the communication ready signal 2 as "0" and the data The second step of receiving the corresponding data of the code and the data value, and outputting the data value of the corresponding data, and the third step of changing the communication ready signal 2 to "1" and outputting it, and then executing another program. Inverter communication method having a plurality of processors, characterized in that made.

※ Note: The disclosure is based on the initial application.