JPH01311615A - Binary data holding circuit - Google Patents

Abstract

PURPOSE:To prevent the chattering and inversion of output generated in the 'H' level of binary data input from occurring by providing a gate at the loop circuit side of a 2:1 selector. CONSTITUTION:The basic constitution of the title circuit is formed by a passing circuit, a holding loop, an inverter 4 comprising the 2:1 selector to select those, and gates 6-8, and a gate circuit 5 is provided at the loop circuit side of the selector. Therefore, binary data output (f) is held at the trailing edge of enable input (b), and the output (c) of the inverter 4 transmits binary data input (a) after the enable input (b) rises and transmission delay, then, holding is released. In such a way, it is possible to prevent the chattering and the inversion due to the transmission delay at a holding loop in the 'H' level of the binary data input (a) from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binary data holding circuit, and particularly to a binary data holding circuit that temporarily stores binary data in a digital circuit such as a digital communication device.

[Conventional technology]

Conventionally, this type of circuit has been constructed as shown in FIGS. 3 and 4. In both countries, the number 9.13 is the binary data input terminal, 10.14 is the enable input terminal, 11.15 is the binary data output terminal, and 12 is the 2 to 1
Selector, 16 is inverter, 17, 18.19 is AN
D gate is shown.

[Problem to be solved by the invention]

The conventional binary data holding circuit described above has a circuit configuration that is affected by the transmission delay caused by the inverter and gate circuit, so the holding output may fluctuate or reverse when holding is performed due to variations in the transmission delay. , it has the disadvantage of low reliability.

This will be explained in detail with reference to FIGS. 4 and 5. FIG. 5 is a timing diagram showing the operation of FIG. 4, taking into account the transmission delay. A signal is input from the data input terminal 13 in FIG. Further, a signal i is input from the i-pull input terminal 14. When the signal i is at the high level, a signal having the same level as the signal 2 is output from the data output terminal 15 as the signal m with only a transmission delay. Further, when the signal i falls, the signal m is output while maintaining the signal level. Furthermore, the signal m is released from being held due to the rise of the signal i, and the signal 11 is output. However, in this circuit, the signal 11
When signal i falls below the 'H' level when signal i falls below the 'H' level, signal k rises. Then, it immediately returns to the °')-1" level.Furthermore, since the signal m has fallen, the -off signal β rises, which causes the signal m to fall.In this way, the binary data is Chattering occurs at high level.

[Means to solve the problem]

The binary data holding circuit of the present invention connects an output to one input to select a loop circuit or a pass circuit, and has a 2-to-1 selector configured by a combination of gates, and a gate transmission when the binary data input is at a high level. This configuration includes a gate circuit that prevents chattering and inversion of binary data output caused by delay, and the gate circuit is provided on the loop circuit side within the selector.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an inverter 4 and a gate) 6, 7.8, which constitute a pass circuit, a holding loop, and a 2-to-1 selector for selecting these, are connected to 1□ (this configuration and a binary It further includes a gate 5 that prevents chattering and inversion due to transmission delay from occurring in the holding loop when the data a is at the top level. This will be explained based on FIG.

Figure 2 is a timing diagram of the circuit in Figure 1.
, a = g in Figure 2 is the signal a of each part of the circuit in Figure 1.
The waveform of ~g corresponds to the waveform of 4y. Assume that the pattern in the binary data a has a signal form as shown in FIG. 2, and the pattern in the enable input signal has a signal form as shown in FIG.

At this time, the output of inverter 4 is signal C, the output of gate 6 is signal d, the output of gate 5 is signal g, the binary data output is signal f, the output of gate 7 is signal e, and the enable input is At the time of falling, the signal f is held, and after the enable signal rises and a transmission delay occurs, the signal C transmits the signal a, and the holding is released.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by adding a gate to the conventional binary data holding circuit configured only with a 2-to-1 selector, chattering and inversion of the output that occur when the binary data input is at the H" level can be suppressed. This can be prevented and the reliability of the binary data holding circuit can be economically increased.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
A timing chart for explaining the operation of the circuit shown in the figure, Figure 3 is a block diagram of a conventional binary data holding circuit, Figure 4 is a circuit diagram corresponding to Figure 3, and Figure 5 is shown in Figure 4. 5 is a timing chart for explaining the operation of the circuit. 1... Binary data input terminal, 2... Enable input terminal, 3... Binary data output terminal, 4...
Inverter, 5, 6, 7.8...gate.

Claims (1)

[Claims] A 2-to-1 selector consisting of a combination of gates that connects the output to one input to select a loop circuit or a pass circuit, and a chattering of the binary data output caused by the transmission delay of the gate when the binary data input is at a high level. 1. A binary data holding circuit comprising: a gate circuit for preventing inversion, the gate circuit being provided on a loop circuit side within the selector.