JPH04213922A - Decode circuit - Google Patents

Decode circuit

Info

Publication number
JPH04213922A
JPH04213922A JP40146390A JP40146390A JPH04213922A JP H04213922 A JPH04213922 A JP H04213922A JP 40146390 A JP40146390 A JP 40146390A JP 40146390 A JP40146390 A JP 40146390A JP H04213922 A JPH04213922 A JP H04213922A
Authority
JP
Japan
Prior art keywords
inputted
output
signal
circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40146390A
Other languages
Japanese (ja)
Inventor
Michinaga Shigiyou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP40146390A priority Critical patent/JPH04213922A/en
Publication of JPH04213922A publication Critical patent/JPH04213922A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent spike noise from being caused in an output signal even when an input signal and a strobe signal are changed simultaneously by devising a decode circuit main body to receive an output of a delay adjustment circuit and providing a strobe input signal input terminal controlling an output signal of the circuit main body on the decode circuit.
CONSTITUTION: Input signals A, B are inputted to a level detection circuit comprising AND gates 1, 3, 4, 6 and its output is inputted to a delay adjustment circuit 7 comprising a delay gate 14 having a delay γ and an OR gate 15. Output signals of level detection circuits 1, 3, 4, 6 are respectively inputted to delay adjustment circuits 2, 5 having a different delay and output signals A', B' are inputted to D, E inputs of a decode circuit 9 with a strobe signal. Then an output signal C' of the delay adjustment circuit 7 is inputted to a strobe signal F of the decode circuit main body with a strobe signal.
COPYRIGHT: (C)1992,JPO&Japio
JP40146390A 1990-12-12 1990-12-12 Decode circuit Pending JPH04213922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40146390A JPH04213922A (en) 1990-12-12 1990-12-12 Decode circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40146390A JPH04213922A (en) 1990-12-12 1990-12-12 Decode circuit

Publications (1)

Publication Number Publication Date
JPH04213922A true JPH04213922A (en) 1992-08-05

Family

ID=18511288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40146390A Pending JPH04213922A (en) 1990-12-12 1990-12-12 Decode circuit

Country Status (1)

Country Link
JP (1) JPH04213922A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842044B1 (en) 2003-10-23 2005-01-11 International Business Machines Corporation Glitch-free receivers for bi-directional, simultaneous data bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842044B1 (en) 2003-10-23 2005-01-11 International Business Machines Corporation Glitch-free receivers for bi-directional, simultaneous data bus

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