KR940016694A - 반도체 소자의 콘택홀 형성방법 - Google Patents

반도체 소자의 콘택홀 형성방법 Download PDF

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Publication number
KR940016694A
KR940016694A KR1019920026905A KR920026905A KR940016694A KR 940016694 A KR940016694 A KR 940016694A KR 1019920026905 A KR1019920026905 A KR 1019920026905A KR 920026905 A KR920026905 A KR 920026905A KR 940016694 A KR940016694 A KR 940016694A
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KR
South Korea
Prior art keywords
contact hole
semiconductor device
formation method
hole formation
peak
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Application number
KR1019920026905A
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English (en)
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KR100244404B1 (ko
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920026905A priority Critical patent/KR100244404B1/ko
Publication of KR940016694A publication Critical patent/KR940016694A/ko
Application granted granted Critical
Publication of KR100244404B1 publication Critical patent/KR100244404B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체 기판(21)에 산화막(23)을 형성한 후 건식식각으로 콘택홀을 메워 형성하고 감광막(24)으로 콘택홀을 메워 장벽을 만들어주는 제 1 단계, 상기 제 1 단계 후에 상기 산화막(23)이 드러나도록 건식식각하여 접촉면(D)과 첨점(C)을 형성하는 제 2 단계, 상기 제 2 단계 후에 상기 접촉면(D)과, 첨점(C)을 습식식각을 하고 상기 감광막(24)을 제거하는 제 3 단계를 구비하고 있는 것을 특징으로 한다.

Description

반도체 소자의 콘택홀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도 내지 제 4 도는 본 발명의 한 실시예의 공정도를 나타낸 단면도.

Claims (1)

  1. 반도체 소자의 콘택홀 형성방법에 있어서, 반도체 기판(21)에 산화막(23)을 형성한 후 건식식각으로 콘택홀을 형성하고 감광막(24)으로 콘택홀을 메워 장벽을 만들어 주는 제 1 단계, 상기 제 1 단계 후에 상기 산화막(23)이 드러나도록 건식식각하여 접촉면(D)과 첨점(C)을 형성하는 제 2 단계, 상기 제 2 단계 후에 상기 접촉면(D)과 첨점(C)을 습식식각을 하고 상기 감광막(24)을 제거하는 제 3 단계를 구비하고 있는 것을 특징으로 하는 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920026905A 1992-12-30 1992-12-30 반도체소자의 콘택홀 형성방법 KR100244404B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026905A KR100244404B1 (ko) 1992-12-30 1992-12-30 반도체소자의 콘택홀 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026905A KR100244404B1 (ko) 1992-12-30 1992-12-30 반도체소자의 콘택홀 형성방법

Publications (2)

Publication Number Publication Date
KR940016694A true KR940016694A (ko) 1994-07-23
KR100244404B1 KR100244404B1 (ko) 2000-02-01

Family

ID=19348054

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026905A KR100244404B1 (ko) 1992-12-30 1992-12-30 반도체소자의 콘택홀 형성방법

Country Status (1)

Country Link
KR (1) KR100244404B1 (ko)

Also Published As

Publication number Publication date
KR100244404B1 (ko) 2000-02-01

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