KR940006362B1 - 반도체 기억장치와 그 동작방법 - Google Patents

반도체 기억장치와 그 동작방법 Download PDF

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Publication number
KR940006362B1
KR940006362B1 KR1019900018940A KR900018940A KR940006362B1 KR 940006362 B1 KR940006362 B1 KR 940006362B1 KR 1019900018940 A KR1019900018940 A KR 1019900018940A KR 900018940 A KR900018940 A KR 900018940A KR 940006362 B1 KR940006362 B1 KR 940006362B1
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KR
South Korea
Prior art keywords
memory cell
data
cell arrays
register means
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019900018940A
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English (en)
Korean (ko)
Other versions
KR910014937A (ko
Inventor
도시유끼 오가와
Original Assignee
미쓰비시 뎅끼 가부시끼가이샤
시기 모리야
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Publication of KR910014937A publication Critical patent/KR910014937A/ko
Application granted granted Critical
Publication of KR940006362B1 publication Critical patent/KR940006362B1/ko
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
KR1019900018940A 1990-01-19 1990-11-22 반도체 기억장치와 그 동작방법 Expired - Fee Related KR940006362B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011496A JP2880547B2 (ja) 1990-01-19 1990-01-19 半導体記憶装置
JP2-11496 1990-01-19

Publications (2)

Publication Number Publication Date
KR910014937A KR910014937A (ko) 1991-08-31
KR940006362B1 true KR940006362B1 (ko) 1994-07-18

Family

ID=11779640

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018940A Expired - Fee Related KR940006362B1 (ko) 1990-01-19 1990-11-22 반도체 기억장치와 그 동작방법

Country Status (4)

Country Link
US (1) US5566371A (enExample)
JP (1) JP2880547B2 (enExample)
KR (1) KR940006362B1 (enExample)
DE (1) DE4022149A1 (enExample)

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JPH05151769A (ja) * 1991-11-28 1993-06-18 Mitsubishi Electric Corp マルチポートメモリ
JPH05225774A (ja) * 1992-02-13 1993-09-03 Mitsubishi Electric Corp マルチポート半導体記憶装置
EP0681279B1 (en) * 1994-05-03 2001-07-18 Sun Microsystems, Inc. Frame buffer random access memory and system
KR0142962B1 (ko) * 1995-05-12 1998-08-17 김광호 계급적 컬럼선택라인구조를 가지는 반도체 메모리 장치
JPH08315567A (ja) * 1995-05-22 1996-11-29 Mitsubishi Electric Corp 半導体記憶装置
JPH09134590A (ja) * 1995-09-04 1997-05-20 Mitsubishi Electric Corp 半導体記憶回路装置及びその設計装置
US5737767A (en) * 1995-11-08 1998-04-07 Advanced Micro Devices, Inc. System for reconfiguring the width of an x-y RAM
TW318933B (en) 1996-03-08 1997-11-01 Hitachi Ltd Semiconductor IC device having a memory and a logic circuit implemented with a single chip
JPH1031886A (ja) * 1996-07-17 1998-02-03 Nec Corp ランダムアクセスメモリ
US5691956A (en) * 1996-07-17 1997-11-25 Chang; Edward C. M. Memory with fast decoding
US5982672A (en) * 1996-10-18 1999-11-09 Samsung Electronics Co., Ltd. Simultaneous data transfer through read and write buffers of a DMA controller
US5717629A (en) * 1996-10-24 1998-02-10 Yin; Ronald Loh-Hwa Memory circuit and method of operation therefor
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5812469A (en) * 1996-12-31 1998-09-22 Logic Vision, Inc. Method and apparatus for testing multi-port memory
US6170046B1 (en) * 1997-10-28 2001-01-02 Mmc Networks, Inc. Accessing a memory system via a data or address bus that provides access to more than one part
US6044030A (en) * 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
US7746701B2 (en) * 2008-01-10 2010-06-29 Micron Technology, Inc. Semiconductor memory device having bit line pre-charge unit separated from data register
JP5731730B2 (ja) * 2008-01-11 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びその半導体記憶装置を含むデータ処理システム
US10602139B2 (en) * 2017-12-27 2020-03-24 Omnivision Technologies, Inc. Embedded multimedia systems with adaptive rate control for power efficient video streaming

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US4450560A (en) * 1981-10-09 1984-05-22 Teradyne, Inc. Tester for LSI devices and memory devices
JPS5956284A (ja) * 1982-09-24 1984-03-31 Hitachi Micro Comput Eng Ltd 半導体記憶装置
US4628480A (en) * 1983-10-07 1986-12-09 United Technologies Automotive, Inc. Arrangement for optimized utilization of I/O pins
US4974199A (en) * 1984-06-28 1990-11-27 Westinghouse Electric Corp. Digital IC-microcomputer interface
US4636986B1 (en) * 1985-01-22 1999-12-07 Texas Instruments Inc Separately addressable memory arrays in a multiple array semiconductor chip
US4855954A (en) * 1985-03-04 1989-08-08 Lattice Semiconductor Corporation In-system programmable logic device with four dedicated terminals
DE3534216A1 (de) * 1985-09-25 1987-04-02 Bayerische Motoren Werke Ag Datenbussystem fuer fahrzeuge
US5109406A (en) * 1985-09-30 1992-04-28 Kabushiki Kaisha Toshiba Call control method and apparatus for a switching system
US4771285A (en) * 1985-11-05 1988-09-13 Advanced Micro Devices, Inc. Programmable logic cell with flexible clocking and flexible feedback
US4817054A (en) * 1985-12-04 1989-03-28 Advanced Micro Devices, Inc. High speed RAM based data serializers
US4758747A (en) * 1986-05-30 1988-07-19 Advanced Micro Devices, Inc. Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor
US5060140A (en) * 1986-01-16 1991-10-22 Jupiter Technology Inc. Universal programmable data communication connection system
CA1293565C (en) * 1986-04-28 1991-12-24 Norio Ebihara Semiconductor memory
US4766593A (en) * 1986-12-22 1988-08-23 Motorola, Inc. Monolithically integrated testable registers that cannot be directly addressed
US5042013A (en) * 1987-05-27 1991-08-20 Hitachi, Ltd. Semiconductor memory
JPH0748301B2 (ja) * 1987-12-04 1995-05-24 富士通株式会社 半導体記憶装置
JP2501344B2 (ja) * 1987-12-26 1996-05-29 株式会社東芝 デ―タ転送回路
JPH0760595B2 (ja) * 1988-01-12 1995-06-28 日本電気株式会社 半導体メモリ
JPH01224993A (ja) * 1988-03-04 1989-09-07 Nec Corp マルチポートメモリ
US4891794A (en) * 1988-06-20 1990-01-02 Micron Technology, Inc. Three port random access memory
JPH0283899A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
JPH02246087A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 半導体記憶装置ならびにその冗長方式及びレイアウト方式
US5001671A (en) * 1989-06-27 1991-03-19 Vitelic Corporation Controller for dual ported memory
US4984214A (en) * 1989-12-05 1991-01-08 International Business Machines Corporation Multiplexed serial register architecture for VRAM
US5028821A (en) * 1990-03-01 1991-07-02 Plus Logic, Inc. Programmable logic device with programmable inverters at input/output pads

Also Published As

Publication number Publication date
DE4022149C2 (enExample) 1993-07-29
JPH03216888A (ja) 1991-09-24
KR910014937A (ko) 1991-08-31
US5566371A (en) 1996-10-15
JP2880547B2 (ja) 1999-04-12
DE4022149A1 (de) 1991-07-25

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