KR940000220B1 - Command word process system of program logic controller - Google Patents

Abstract

The system includes a command latch unit (7) for inputting the command of a program memory (3), an OR-gate (OR1) for oring the clock signal of a clock generator (6) and hardware run signal (HRS), an OR-gate (OR1) for oring the read signal (RD) and enable signal (EN), a buffer unit (4) for buffering the command of a command latch unit (7), an AND-gate (AND1) for driving the clock pulse to a command pointer counter unit (2) and command latch unit (7). This system improves the processing time.

Description

Instruction Processing System of Program Logic Controller

1 is a block diagram of an instruction processing system of a conventional program logic controller.

2 is a signal flow diagram for the description of the operation of FIG.

3 is a configuration diagram of an instruction processing system of the program logic controller of the present invention.

4 is a signal flow diagram for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

1: central processing unit 2: instruction pointer counter

3: user program memory section 4: buffer section

5: hardware instruction execution unit 6: clock generator

7: Instruction latch OR1, OR2: Oagate

AND1: ANDGATE

The present invention is to improve the user program execution speed of the programmable logic controller, in particular, when the central processing unit reads an instruction to be executed when executing a soft instruction, the time delay according to the operation of the pointer and address of the instruction The present invention relates to a command processing system of a program logic controller for fast processing in general in hardware and software.

As shown in FIG. 1, the software processing system of the conventional program logic controller includes a central processing unit 1 and a central processing unit 1 for controlling the overall system operation according to the program execution of the program ROM 9. Selects the instruction pointer counter 2 for counting the instruction point IP output from the < RTI ID = 0.0 >), < / RTI > the address signal output from the CPU 1 and the instruction pointer IP of the instruction pointer counter 2; An address selector 7, a user program memory unit 3 for outputting an application program of a corresponding user stored in accordance with the address designation of the address selector 7, and hardware input of the central processing unit 1; A hardware instruction that is enabled by the enable signal HEN and is performed in hardware by synchronizing the instruction of the user program memory unit 3 with the clock pulse of the clock generator 6. A row section 5, a data memory section 8 for storing data processed by the hardware instruction execution section 5, and a hardware run signal HRS and a clock generation section output from the hardware instruction execution section 5; The AND gate AND1 inputs the clock pulse of (6) to the instruction pointer counter section 2, and the user program memory section 3 when the software run signal SRS is generated from the hardware instruction execution section 5; It is composed of a buffer unit (4) for buffering the command of () and input to the central processing unit (1).

The command processing system of the conventional program logic controller configured as described above will be described with reference to FIG.

As shown in FIG. 2, the central processing unit 1 initially initializes the instruction pointer counter unit 2 according to the program execution of the program ROM 9, and then enables hardware in the hardware instruction execution unit 5. The signal HEN is applied to enable it. The hardware command execution unit 5 executes the user's command output from the user program memory unit 3 in synchronization with the clock pulse of the clock generation unit 6, and performs a " 1 " of the hardware run signal HRS. The AND gate AND1 is applied to the gate AND1, and the AND gate AND1 ANDs the clock pulse generated from the clock generator 6 and the hardware run signal HRS output from the hardware instruction execution unit 5 to command the instruction. It is applied to the clock terminal of the pointer counter 2. Accordingly, the instruction pointer counter 2 counts clock pulses input from the AND gate AND1 to increase the instruction pointer IR by one, and then the address of the user program memory unit 3 through the address selector 7. By inputting the next command to the hardware command execution unit (5). During the execution of a series of hardware instructions in this manner, the hardware instruction execution section 5, in which an instruction that cannot be executed by hardware is input from the user program memory section 3, clocks the hardware run signal HRS as " ψ ". The output clock pulses of the generator 6 and the AND gate AND1 are stopped, and the software run signal SRS is applied to the central processing unit 1. At this time, when the CPU 1 reads a command to be executed by software, a method of operating the instruction pointer IR as shown in FIG. 2A and a user program memory unit as shown in FIG. 2B. It reads in the method of operating the address of (3).

That is, when the instruction point IR is manipulated and read as shown in FIG. 2A, the CPU 1 first reads the current instruction pointer IR from the instruction pointer counter 2. In addition, the instruction of the user program memory unit 3 buffered from the buffer unit 4 is read and processed, and a clock pulse is applied to the instruction pointer counter unit 2 to increase the pointer IP by one. . Accordingly, the instruction pointer counter section 2 designates the address of the user program memory section 3 through the address selection section 7 and inputs the next command to the buffer section 4, and the buffer section 4 inputs The command is buffered and input to the CPU 1. In this way, the central processing unit 1 increments the instruction pointer IR by one, reads and executes a series of user instructions through the buffer unit 4, and then positions the instruction pointer to be executed next. ) And the hardware enable signal HEN is applied to the hardware instruction execution unit 5 to process the execution of the next instruction in hardware. On the other hand, when the address of the user program memory unit 3 is read and manipulated as shown in FIG. 2B, the CPU 1 receives the software run signal SRS from the hardware command execution unit 5 first. ) Reads the current instruction pointer IR from the instruction pointer counter section 2, converts an address to designate the user program memory section 3, and then converts the address of the user program memory section 3 through the address selection section 7. The next command is input to the buffer unit 4 by designating an address, and the buffer unit 4 buffers the input command and inputs it to the central processing unit 1. In this way, the central processing unit 1 increments the addresses one by one, reads and executes a series of user instructions through the buffer unit 4, and then sets the next instruction position to be executed in the instruction pointer counter unit 2. The hardware enable signal HEN is applied to the hardware command execution unit 5 to process the execution of the next command in hardware.

However, such a command processing system of a conventional program logic controller requires a command pointer operation of an instruction pointer counter unit or an address operation of a user program memory unit to read a user's command to be executed by software, such that The time delay consumed in the system has a problem in that the efficiency of the system is reduced in view of the hardware command execution unit.

SUMMARY OF THE INVENTION In view of such a conventional problem, the present invention provides a central processing unit for executing instructions when executing a software instruction by using an instruction latch unit for latching an instruction of a user program memory unit, and an oragate providing an enable signal of a clock pulse and a buffer unit. In order to solve the time delay caused by the operation of the pointer and the address of the instruction to read the invention, the present invention is described in detail with reference to the accompanying drawings, the invention of the instruction logic system of the program logic controller.

3 is a configuration diagram of a command processing system of the program logic controller of the present invention. As shown therein, a central processing unit 1 for controlling the overall operation of a system in accordance with a program execution of a program ROM 9, and the central processing unit A user pointer memory for outputting an instruction pointer counter section 2 for counting step information of the user program outputted from (1) and an application program of the user stored according to the step information of the instruction pointer counter section 2; By the hardware enable signal HEN of the CPU 3, the instruction latch unit 7 for latching the corresponding instruction of the user output from the user program memory unit 3, and the CPU 1; Hardware command execution, which is enabled and is performed in hardware by synchronizing the user's command output from the command latch unit 7 with the clock pulse of the clock generator 6 (5), a data memory section 8 for storing data processed by the hardware command execution section 5, a hardware run signal (HRS) and a clock generation section output from the hardware command execution section 5 ( OA gate OR1 for ringing and outputting the clock pulse of 6) and enable signal EN outputted from the central processing unit 1 when the software run signal SRS is generated from the hardware command execution unit 5. And a buffer for buffering a user command of the instruction latch unit 7 according to the output signal of the ora gate OR2 and the read signal RD, and inputting the read signal RD to the CPU 1. And an AND gate AND1 for supplying clock pulses to the instruction pointer counter unit 2 and the instruction latch unit 7 by ANDing the output signals of the OR gates OR1 and OR2. .

Referring to the operation and effects of the present invention configured as described above are as follows.

Initially, the central processing unit 1 initializes the instruction pointer counter unit 2 according to the program execution of the program ROM 9, and then records the step information of the user program in the instruction pointer counter unit 2. Accordingly, the instruction pointer counter section 2 designates the corresponding address of the user program memory section 3, and the instruction of the corresponding step is output from the user program memory section 3 and input to the instruction latch section 7. Thereafter, the central processing unit 1 applies the hardware enable signal HEN to the hardware command execution unit 5 to enable it. At this time, after the NOP instruction, which is initially latched in the instruction latch unit 7, is executed, the instruction of the first user from the user program memory unit 3 is latched to the instruction latch unit 7 to execute a hardware instruction. The hardware command execution unit 5 enabled by the central processing unit 1 when inputted to the unit 5, if the user's command output from the instruction latch unit 7 can be executed in hardware, The user's command is executed in synchronization with the clock pulse of the clock generator 6, and the hardware run signal HRS is set to " 1 " and applied to the input inverting terminal of the oragate OR1. ) Outputs the clock pulse to one input terminal of the AND gate AND1 by ringing the clock pulse generated from the clock generator 6 and the hardware run signal HRS. At this time, the central processing unit 1 applies the read signal RD high to the other input terminal of the AND gate AND1 through the OR gate OR2, so that the AND gate AND1 is connected to the OR gate OR1 ( The output signal of OR2) is ANDed to apply a clock pulse to the clock terminal of the instruction pointer counter section 2 and the clock terminal of the instruction latch section 7. Accordingly, the instruction pointer counter unit 2 counter-clocks up the clock pulse output from the AND gate AND1, and then designates an address with the user program memory unit 3 to input the next instruction to be executed into the instruction latch unit 7. In addition, the instruction latch unit 7 latches the instruction of the user program memory unit 3 in synchronization with the clock pulse of the AND gate AND1 and inputs it to the hardware instruction execution unit 5. If an instruction that cannot be executed by hardware is input from the instruction latch section 7 while executing a series of hardware instructions in this manner, the hardware instruction execution section 5 sets the hardware run signal HRS to " ψ " The output clock pulse of the gate AND1 is stopped and the software run signal SRS is applied to the CPU 1. At this time, the central processing unit 1 sets the read signal RD and the enable signal EN as a low signal without manipulating the user program memory unit 3 and the instruction pointer counter unit 2 to perform the OR gate OR2. Through the buffer unit 4 is enabled. Accordingly, the buffer unit 4 buffers the user's command output from the instruction latch unit 7, and the central processing unit 1 reads the user's command buffered from the buffer unit 4 and reads the signal. (RD) is made high and applied to one input terminal of the AND gate AND1 through the OR gate OR2. Therefore, the AND gate AND1 ANDs the high signal output from the OR gate PR1 and the read signal RD through the OR gate OR2 to the instruction latch unit 7 and the instruction pointer counter unit 2. After inputting the clock pulse, the instruction pointer counter unit 2 counts up the clock pulse output from the AND gate AND1, and then designates the address of the user program memory unit 3 to execute the next instruction to be executed. (7) is latched.

As such, when the processing of the software command is completed, the CPU 1 applies the hardware enable signal HEN to the hardware command execution unit 5 to process the execution of the next command in hardware.

As described in detail above, the present invention eliminates time delay caused by address manipulation of a pointer and a user program memory unit by adding an instruction latch unit and an oragate when the central processing unit reads an instruction to be executed when executing a software instruction. It is effective to process soft instructions at high speed.

Claims (1)

In response to the enable signal of the central processing unit 1, the hardware instruction execution unit 5 increases the count of the instruction pointer counter unit 2 to the program logic controller for processing the instruction of the user program memory unit 3. In addition, the instruction latch unit 7 for latching a user's command output from the user program memory unit 3 and inputting it to the hardware command execution unit 5, and the hardware run output from the hardware command execution unit 5 Oaring OR1 for ringing the signal HRS and the clock signal of the clock generator 6, and ringing the enable signal EN and the read signal RD outputted from the central processing unit 1; A buffer unit 4 which is enabled according to the OR gate OR2 and the output signal of the OR gate OR2 and buffers the instruction of the instruction latch unit 7 and inputs the CPU 1 to the CPU 1; Output signal of the gate OR1 or OR2 And-granulation to instruction pointer counter unit 2 and the command latch section 7, the clock AND gate a program instruction processing system of the logic controller characterized in that it consists of (AND1) for providing a pulse to.