JPH0535469A - Programmable controller - Google Patents

Abstract

PURPOSE:To speed up the processing speed of the entire sequence processing. CONSTITUTION:The programmable controller is provided with an execution/ nonexecution discrimination circuit 5 discriminating whether a sequence instruction which receives the former processing result from a processor 1 for sequence instruction processing as a status S and is read out this time is to be executed or not in the processor 1 for sequence instruction processing, dummy instruction register 8 storing a dummy instruction DD, and a multiplexer 9 selecting a micro instruction from a microprogram memory 3 in the case an execution signal is outputted from the execution/nonexecution discrimination circuit 5 and selecting a dummy instruction DD of a dummy instruction register 8 in the case an nonexecution signal is outputted from the execution/nonexecution discrimination circuit 5 to be supplied to the processor 1 for sequence instruction processing. Thus, the amount of microprogram can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applicable to sequence control in sequence control adopted in production lines of various factories.
More specifically, the present invention relates to a programmable controller for executing a program, which is improved so as to improve the processing speed of a processor for processing a sequence instruction that executes each sequence instruction in a sequence program.

[0002]

2. Description of the Related Art A main part of a programmable controller adopted in the field of sequence control is shown in a block diagram of FIG. 8 and its operation is shown in a flowchart of FIG. In FIG. 8, a conventional programmable controller includes a sequence instruction processing processor 1 including a microprocessor and the like, a sequence program memory 2 for storing a sequence program including each sequence instruction, and a micro instruction corresponding to the sequence instruction. The sequence instruction processing processor 1 includes an address bus, a data bus, a control memory 3 and a working memory 4 that stores data used for processing and is also used as a work area.・ Connect to each block by bus.

The operation of such an apparatus will be described with reference to the block diagram of FIG. 8 and the flowchart of FIG. The sequence instruction processing processor 1 sends out the address AP, fetches the sequence instruction DP from the sequence program memory 2, and then sends out the address AM corresponding to the sequence instruction DP to the microprogram memory 3. The sequence instruction is processed by fetching the micro instruction DM and executing the micro instruction DM. At this time, depending on the type of the fetched sequence instruction, the execution / execution of the sequence instruction is executed depending on the previous sequence processing result (bit operation processing result).
There is something that must be determined to be non-execution, and this execution / non-execution determination is made by the sequence instruction processing processor
In such a method, the bit information (bit operation processing result) stored in the accumulator or the like is checked. Then, when the non-execution is determined, the address AP for fetching the next sequence instruction is transmitted.
When the execution instruction is determined, the microinstruction DM corresponding to this sequence instruction DP is fetched and executed. A plurality of micro instructions may correspond to one sequence instruction.

As described above, in order to process a sequence program, a sequence instruction is sequentially fetched, a determination as to whether or not to execute is made by software, and a microinstruction group corresponding to this sequence instruction is fetched. By doing. Therefore, in order to execute one sequence instruction, it is necessary to perform several steps of processing in the sequence instruction processing processor 1, and there is a problem that the processing time of the entire sequence program becomes long.

As a solution to this problem, there is a structure as shown in FIG. This example uses the sequence
Sequence command D sent from the program memory 2
An execution / non-execution determination circuit 5 is provided which receives P and receives the previous sequence processing result (bit operation processing) in the sequence instruction processing processor 1 as status S. With this execution / non-execution determination circuit 5,
The execution / non-execution of the sequence instruction fetched this time can be determined at high speed by hardware. Further, the microprogram memory address AR sent from the sequence instruction processing processor 1 at the time of non-execution is stored in the non-execution time address register 6, and the non-execution time microprogram memory address AR and the sequence instruction processing are processed. The address AM from the processor 1 is applied to the multiplexer 7. The multiplexer 7 is given an execution / non-execution instruction signal E / D from the execution / non-execution determination circuit 5, selects the address AM from the sequence instruction processing processor 1 at the time of execution determination, and outputs the non-execution at the time of non-execution determination. The non-execution time microprogram memory address AR stored in the execution time address register 6 is selected and given to the microprogram memory 3 as the read address AI.

FIG. 11 is a time chart showing the operation of the example of the apparatus shown in FIG. In this figure, one cycle T of the operation clock CP corresponds to the time for executing one sequence instruction, and the execution / non-execution instruction signal E / D is “H” at the beginning, and the microprogram memory is switched by switching the multiplexer 6. 3 is a processor for processing sequence instructions 1
The address AM from is given. Then, at the first time t1 of the next cycle, the execution / non-execution judging circuit 5 judges that this sequence instruction is a non-execution instruction, and outputs the execution / non-execution instruction signal E / D “L”. Then, the multiplexer 7 gives the address AR stored in the non-execution time address register 6 to the microprogram memory 3. The address AR designates a microinstruction instructing non-execution in the microprogram memory 3, and the sequence instruction processing processor 1 fetches the microinstruction DM instructing nonexecution and fetches the next sequence instruction. To work.

[0007]

By the way, in FIG. 11, the time T for executing one sequence instruction is the time t1 required for execution / non-execution determination in the execution / non-execution determination circuit 5 and the micro time indicating the non-execution. This is the sum of the memory access time t2 for reading an instruction, but even if the memory access time t2 is shortened by using a high-speed memory for the microprogram memory 3, the execution / non-execution determination time t1
Is a constant and always required time, and this extra time t
The stacking of 1 causes a problem that the improvement of the processing speed of the entire sequence processing is hindered.

An object of the present invention is to solve such a problem, and an object thereof is to speed up the processing speed of each sequence instruction, thereby speeding up the processing speed of the entire sequence processing.

[0009]

According to the present invention, which has solved the above-mentioned problems, a sequence instruction processing processor, a sequence program memory in which a sequence program is stored, and each sequence constituting the sequence program are provided. A microprogram memory storing microinstructions corresponding to the instructions, the sequence instruction processing processor sequentially reads the sequence instructions from the sequence program memory, and outputs microinstructions corresponding to the sequence instructions to the microprogram.
In a programmable controller that reads out from a memory and executes sequence processing, the sequence instruction read out this time is received by the sequence instruction processing processor as status and executed by the sequence instruction processing processor. An execution / non-execution judging circuit for judging whether there is an execution or non-execution, a dummy instruction register for storing a dummy instruction, and the micro program if an execution signal is outputted from the execution / non-execution judging circuit. A multiplexer for selecting a microinstruction from a memory and, when a non-execution signal is output from the execution / non-execution determination circuit, selecting a dummy instruction in the dummy instruction register and giving it to the sequence instruction processing processor. Featured programmable controller A.

[0010]

In the programmable controller of the present invention, when the execution signal is output from the execution / non-execution determination circuit, the micro instruction from the microprogram memory is selected and the non-execution signal is output from the execution / non-execution determination circuit. When it is output, the dummy instruction in the dummy instruction register is selected and given to the sequence instruction processing processor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an example of a programmable controller embodying the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the programmable controller of the present invention.
In this figure, the same reference numerals as those of the conventional programmable controller shown in FIGS. 8 and 10 have the same functions. The programmable controller of the present invention is characterized in that a dummy instruction register 8 for storing a dummy instruction DD having the same meaning as a micro instruction representing non-execution of a sequence instruction, the dummy instruction DD, and the micro program memory 3 are used. A microinstruction DM and a multiplexer 9 for selecting an instruction DI as an output from the execution / non-execution determination signal E / D from the execution / non-execution determination circuit 5 and providing the instruction DI to the sequence instruction processing processor 1 are provided. is there.

The operation of the programmable controller of the present invention thus constructed will be described with reference to the block diagram of FIG.
This will be described with reference to the flowchart of FIG. The sequence instruction processing processor 1 fetches the sequence instruction DP from the sequence program memory 2, and the sequence instruction DP is given to the execution / non-execution determination circuit 5.
The execution / non-execution determination circuit 5 receives the given sequence command DD and the previous processing result status S from the sequence command processing processor 1 and receives the current sequence command D.
The execution / non-execution of P is determined. If it is determined to execute,
Address A corresponding to the fetched sequence instruction DP
While M is given from the sequence instruction processing processor 1 to the microprogram memory 2, the execution / non-execution determination circuit 5 outputs the execution / non-execution determination signal E / D "H", and the multiplexer 9 is the micro program memory. Select the microinstruction DM of 3 and select this microinstruction DM
Is given to the sequence instruction processing processor 1 as an instruction DI. After that, the same processing as the conventional one proceeds. If it is determined to be non-execution, execution / non-execution determination signal E / D “L”
Is output and the multiplexer 9 outputs the dummy instruction register 8
Output DD of the above is selected, and this dummy instruction DD is given to the sequence instruction processing processor 1 as the instruction DI. The sequence instruction processing processor 1 uses the dummy instruction DD
, The sequence instruction is not executed and the next sequence instruction is fetched.

FIG. 3 is a time chart showing a specific operation of the programmable controller of the present invention as described above. When the fetched sequence instruction is executed in the first cycle, the execution / non-execution judging circuit 5 judges that the instruction is executed, the execution / non-execution instruction signal E / D “H” is maintained, and the multiplexer 9 is set in the microprogram memory. 3 output DM side is selected. On the other hand, the address AM1 designating the microinstruction corresponding to this sequence instruction
Are given to the microprogram memory 2, and the corresponding microinstruction DM1 is given to the sequence instruction processing processor 1 via the multiplexer 9. In the next cycle, with respect to the fetched sequence instruction, the corresponding address AM2 is sent to the microprogram memory 3, while the execution / non-execution judging circuit 5 judges as non-execution, execution / non-execution. The execution instruction signal E / D becomes "L", and the multiplexer 9 switches to output the output DD of the dummy instruction register 8. As a result, the sequence instruction processing processor 1
Irrespective of the access to the microprogram memory 3, the dummy instruction DD is immediately fetched and the corresponding processing is performed. Next, when the fetched sequence instruction is determined to be executed, the execution / non-execution instruction signal E / D
It becomes "H", and the multiplexer 9 selects the microinstruction DM3 corresponding to the address AM3 sent from the sequence instruction processing processor 1. As shown in FIG. 3, in the programmable controller of the present invention, the cycle T'where one sequence instruction is executed
The non-execution determination time t3 and the time t4 corresponding to the time required to fetch the dummy instruction DD or the time required to fetch the data (microinstruction DM) corresponding to the address AM after the elapse of t3 may be considered. Run /
The non-execution determination time t3 may be included in the access time T ′ for the microprogram memory 3 of the sequence instruction processing processor 1. That is, the cycle T ′ in which one sequence command is executed is a time that depends only on the access time to the microphone program memory 3. Therefore, one period T'of the programmable controller of the present invention is
It can be shorter than one cycle T in the conventional device shown in FIG.

Next, a sequence instruction targeted by the present invention for explaining an outline when an actual sequence program is executed is a ladder sequence program as shown in FIG. 4, which is a mnemonic expression of the ladder sequence program. Figure 5
Shown in. For example, the program instruction on the first line in FIG. 4 is to execute the instruction “MOV D001 D008” when the contact X00501 is on “1” and the contact X00316 is on “1”, and the same applies to the second and subsequent lines. .. FIG. 6 shows a contact X00501 on "1" and a contact X00316 on "1". This state "1" is stored in the accumulator ACC.
This is a case where the data is stored in and processing is continued. The accumulator ACC "1" corresponds to the status S in the sequence instruction processing processor 1, and the multiplexer 9 maintains the output selection of the microprogram memory 3. FIG. 7 shows a contact X00501 on “1”, a contact X0.
0316 is off "0", and shows the case where the content of the accumulator ACC is switched from "1" to "0", whereby the multiplexer 9 selects the output of the dummy instruction register 8 (dummy instruction DD). Switch. In this way, when the sequence command is executed, the external appearance is the same as the conventional one, and the high-speed processing can be realized.

[0015]

As described above, according to the programmable controller of the present invention, execution / non-execution of the fetched sequence instruction is determined by hardware.
This determination processing can be shortened as compared with the method of processing by software by a micro program, and the entire processing time of the sequence program can be significantly shortened.
Furthermore, since the determination process by the microprogram is omitted, the amount of the microprogram can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a programmable controller embodying the present invention.

FIG. 2 is a flowchart showing the operation of the programmable controller of the present invention.

FIG. 3 is a time chart showing the operation of the programmable controller of the present invention.

FIG. 4 is an example of a ladder program targeted by the programmable controller of the present invention.

FIG. 5 is an example of a mnemonic expression of the ladder program shown in FIG.

FIG. 6 is a diagram showing a case where the instruction sequence of FIG. 5 is executed in the programmable controller of the present invention.

FIG. 7 is a diagram showing a case where the instruction sequence of FIG. 5 is executed in the programmable controller of the present invention.

FIG. 8 is a diagram showing a conventional programmable controller.

9 is a flowchart showing an operation of the conventional programmable controller shown in FIG.

FIG. 10 is a diagram showing a conventional programmable controller.

FIG. 11 is a time chart showing the operation of a conventional programmable controller.

[Explanation of symbols]

 1 processor for sequence instruction processing 2 sequence program memory 3 micro program memory 4 working memory 5 execution / non-execution determination circuit 6 non-execution time address register 7, 9 multiplexer 8 dummy instruction register

Claims (1)

Claim: What is claimed is: 1. A sequence instruction processing processor, a sequence program memory in which a sequence program is stored, and a micro instruction corresponding to each sequence instruction forming the sequence program. The sequence instruction processing processor sequentially reads the sequence instructions from the sequence program memory, reads the corresponding micro instructions from the micro program memory, and executes the sequence processing. A programmable controller that receives the result of previous processing from the sequence instruction processing processor as status and executes the sequence instruction read this time in the sequence instruction processing processor. An execution / non-execution judging circuit for judging whether there is an execution or non-execution, a dummy instruction register for storing a dummy instruction, and the micro program if an execution signal is outputted from the execution / non-execution judging circuit. A multiplexer for selecting a microinstruction from a memory and, when a non-execution signal is output from the execution / non-execution determination circuit, selecting a dummy instruction in the dummy instruction register and giving it to the sequence instruction processing processor. Characteristic programmable controller.