KR930017110A - 수소 라디칼을 포함하는 반응성 이온 부식 공정 - Google Patents

수소 라디칼을 포함하는 반응성 이온 부식 공정 Download PDF

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KR930017110A
KR930017110A KR1019930000771A KR930000771A KR930017110A KR 930017110 A KR930017110 A KR 930017110A KR 1019930000771 A KR1019930000771 A KR 1019930000771A KR 930000771 A KR930000771 A KR 930000771A KR 930017110 A KR930017110 A KR 930017110A
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gas mixture
dielectric
reactive gas
layer
semiconductor layer
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메흐다드 함라 매트
윌리암 힐스 그래함
제임스 모리 이안
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제임스 조셉 드롱
어플라이드 머티어리얼스, 인코포레이티드
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/3266Magnetic control means
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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Abstract

수소, 암모니아 또는 메탄과 같은 수소 라디칼의 가스원을 총 가스 유동의 약 5내지 20부피 퍼센트의 양으로 산화물 RIE부식용 화학물질에 추가하면, 다 실리콘의 부식율은 억제되는 반면에 산화물의 부식율은 증가할 것이다. 이러한 효과는 낮은 웨이퍼 온도에서 보다 두드러진다. 새로운 공정 화학물질은 형상 각(profile angle), RIE래그(lag)및 부식을 균등도에 해로운 영향을 끼치지 않으면서 산화물 부식율을 5000A°/mon이상으로 증가시키고, 다 실리콘에 대한 선택성을 25 : 1보다 크게 개선시킨다. 화학물질 CHF3, Ar,CF4및 가스 유동의 10부피 퍼센트를 구성하는 NH3를 사용하여 15%보다 작은 RIE래그(lag)와 함께 50 : 1의 선택성이 달성되었다.

Description

수소 라디칼을 포함하는 반응성 이온 부식 공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실행에 적합한 플라즈마 부식 장치의 투시도, 제2도는 제1도에 도시된 플라즈마 부식 장치의 단면도, 제3도는 본 발명에 따른 반응성 이온 부식 공정의 실행을 통해얻은 결과를 나타내는 그래프.

Claims (25)

  1. 반응성 이온 부식 방법으로서 폐쇄된 챔버에서 기질의 표면상에 적어도 하나의 유전체층 및 반도체층을 포함하는 구조물을 위치시키는 단계와, 수소 라디칼의 가스원을 포함하는 선택된 반응성 가스 혼합물을 상기 챔버에 제공하는 단계와, 상기 기질의 표면에 대하여 수직한 연관된 전기장 및 부식용 플라즈마를 조성하도록 RF에너지를 상기 챔버에 가하는 단계와, 상기 전기장에 대하여 수직하고 상기 기질의 표면에 대하여 평행한 직류 자기장을 상기 챔버에 가하는 단계와, 그리고 반응성 가스 혼합물이 유전체층 또는 반도체 층의 적어도 일부분을 부식시킬 수 있도록 하는 단계를 포함하는 방법.
  2. 제1항에 있어서, 유전체층 또는 반도체층에 차폐층을 바르는 단계 및 적어도 하나의 개구부를 통해서 유전체층 또는 반도체층이 노출되도록 차폐층에 적어도 하나의 개구부를 형성하는 단계를 더 포함하는 방법.
  3. 제1항에 있어서, 수소 라디칼의 가스원이 수소, 암모니아 또는 메탄을 포함하는 방법.
  4. 제3항에 있어서, 수소 라디칼의 가스원 암모니아를 포함하는 방법.
  5. 제4항에 있어서, 반응성 가스 혼합물이 약 5 내지 20부피 퍼센트의 암모니아를 포함하는 방법.
  6. 제5항에 있어서, 반응성 가스 혼합물이 약 10부피 퍼센트의 암모니아를 포함하는 방법.
  7. 제4항에 있어서, 반응성 가스 혼합물이 CHF3및 아르곤을 더 포함하는 방법.
  8. 제7항에 있어서, 반응성 가스 혼합물이 CF4또는 C2F6를 더 포함하는 방법.
  9. 제1항에 있어서, 상기 유전체층이 실리콘 산화물층으로 이루어져 있는 방법.
  10. 제1항에 있어서, 상기 반도체층이 실리콘층으로 이루어져 있는 방법.
  11. 제1항에 있어서, 반응성 가스 혼합물이 유전체층 또는 반도체 층의 적어도 일부분을 부식시키기 전에 음극에서의 온도를 약 40℃내지 20℃범위로 조성하는 단계를 더 포함하며, 상기 기질이 상기 챔버의 음극에 위치하는 방법.
  12. 제11항에 있어서, 상기 음극에서의 온도가 약 0℃내지 20℃의 범위로 조성되는 방법.
  13. 유전체 또는 반도체를 부식시키기 위한 반응성 이온 부식 방법으로서, 유전체 또는 반도체에 대한 반응성 수소 라디칼의 가스원을 반응성 가스 혼합물에 추가하는 단계를 포함하는 방법.
  14. 제13항에 있어서, 유전체층 또는 반도체층에 차폐층을 바르는 단계, 및 적어도 하나의 개구부를 통해서 유전체층 또는 반도체층이 노출되도록 차폐층에 적어도 하나의 개구부를 형성하는 단계를 더 포함하는 방법.
  15. 제13항에 있어서, 수소 라디칼의 가스원이 수소, 암모니아 또는 메탄을 포함하는 방법.
  16. 제15항에 있어서, 수소 라디칼의 가스원이 암모니아를 포함하는 방법.
  17. 제16항에 있어서, 반응성 가스 혼합물이 약 5 내지 20부피를 퍼센트의 암모니아를 포함하는 방법.
  18. 제17항에 있어서, 반응성 가스 혼합물이 약 10부피 퍼센트의 암모니아를 포함하는 방법.
  19. 제16항에 있어서, 반응성 가스 혼합물이 CHF3및 아르곤을 더 포함하는 방법.
  20. 제19항에 있어서, 반응성 가스 혼합물이 CF4또는 C2F6를 더 포함하는 방법.
  21. 제13항에 있어서, 유전체층이 실리콘 산화물층으로 이루어져 있는 방법.
  22. 제13항에 있어서, 반도체층이 실리콘층으로 이루어져 있는 방법.
  23. 제13항에 있어서, 반응성 가스 혼합물이 유전체 또는 반도체층의 적어도 일부분을 부식시키기 전에 음극에서의 온도를 약 -40℃내지 20℃범위로 조성하는 단계를 더 포함하며, 기질이 상기 챔버의 음극에 위치하는 방법.
  24. 제23항에 있어서, 상기 음극에서의 온도가 약 0℃ 내지 20℃의 범위로 조성되는 방법.
  25. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930000771A 1992-01-29 1993-01-21 수소라디칼을포함하는반응성이온에칭방법 KR100305508B1 (ko)

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US07/827,377 US5242538A (en) 1992-01-29 1992-01-29 Reactive ion etch process including hydrogen radicals
US07/827,377 1992-01-29

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