KR930006915A - Capacitor Manufacturing Method of Semiconductor Memory Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Memory Device Download PDF

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Publication number
KR930006915A
KR930006915A KR1019910016078A KR910016078A KR930006915A KR 930006915 A KR930006915 A KR 930006915A KR 1019910016078 A KR1019910016078 A KR 1019910016078A KR 910016078 A KR910016078 A KR 910016078A KR 930006915 A KR930006915 A KR 930006915A
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KR
South Korea
Prior art keywords
oxide film
polysilicon
photoresist
node
etching
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Application number
KR1019910016078A
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Korean (ko)
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KR940001255B1 (en
Inventor
서현환
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019910016078A priority Critical patent/KR940001255B1/en
Publication of KR930006915A publication Critical patent/KR930006915A/en
Application granted granted Critical
Publication of KR940001255B1 publication Critical patent/KR940001255B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명을 반도체 메모리 소자의 캐패시터 제조방법에 관한 것으로 특히 게이트 형성시 노드 폴리 실리콘 중 일부를 미리 형성시켜 캐패시터 용량을 증대시킨 캐패시터 제조방법에 관한 것이다. 이를 위하여 본 발명의 방법은, 실리콘 기판 위에 필드 산화막을 형성하고, 게이트 폴리 실리콘, 캡 산화막, 제1폴리 실리콘 및 제1산화막을 형성하는 단계(a)와, 게이트를 식각하고 전면에 얇은 질화막을 증착시킨 다음, 이 질화막을 에치 백 한 후 제1폴리 실리콘 위에 제1산화막을 제거하는 단계와(b), 제2산화막을 입힌 후 사이드 월을 형성하고 다시 제3산화막을 입힌 후 베리드 콘택 마스크를 정의하는 단계 (c)와, 베리드 콘택을 식각한 후 노드 폴리 실리콘을 증착하고 노드 마스크를 정의하는 단계(d)와, 노드 폴리 실리콘을 식각하고 노드 마스크를 제거한 후 포토 레지스트를 코팅하는 단계(e)와, 이 포토레지스트를 캡 산화막위의 제1폴리실리콘이 나올때까지 에치 백 한 후, 포토 레지스트 위의 제2산화막을 습식 또는 건식 에치로 제거하고 포토 레지스트를 제거하는 단계(f)를 구비하는 것을 특징으로 한다.The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor in which a part of the node polysilicon is formed in advance to increase the capacity of a capacitor. To this end, the method of the present invention comprises the steps of (a) forming a field oxide film on a silicon substrate, forming a gate polysilicon, a cap oxide film, a first polysilicon and a first oxide film, etching the gate, and forming a thin nitride film on the entire surface. After the deposition, the nitride film is etched back and then the first oxide film is removed on the first polysilicon (b), the second oxide film is coated, the sidewall is formed, and the third oxide film is coated again. Defining (c), depositing the node polysilicon after etching the buried contact, and defining the node mask (d), and etching the node polysilicon and removing the node mask, coating the photoresist. (e) and the photoresist were etched back until the first polysilicon on the cap oxide film came out, and then the second oxide film on the photoresist was removed by wet or dry etch and the photoresist was removed. It characterized in that it comprises a step (f) to remove the bit.

Description

반도체 메모리 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 캐패시터 제조공정을 도시한 도면.2 is a view showing a capacitor manufacturing process of the present invention.

Claims (1)

반도체 메모리 소자의 캐패시터 제조방법에 있어서 실리콘 기판위에 필드 산화막을 형성하고, 게이트 폴리 실리콘, 캡 산화막, 제1폴리 실리콘 및 제1산화막을 형성하는 단계(a)와, 게이트를 식각하고 전면에 얇은 질화막을 증착시킨 다음, 이 질화막을 에치 백 한 후 제1폴리 실리콘 위에 제1산화막을 제거하는 단계와(b), 제2산화막을 입힌 후 사이드 월을 형성하고 다시 제3산화막을 입힌 후 베리드 콘택 마스크를 정의하는 단계(c)와, 베리드 콘택을 식각한 후 노드 폴리 실리콘을 증착하고 노드 마스크를 정의하는 단계(d)와, 노드 폴리 실리콘을 식각사고 노드 마스크를 제거한 후 포토 레지스트를 코팅하는 단계(e)와, 상기 포토레지스트를 캡 산화막위의 제1폴리실리콘이 나올때까지 에치 백 한 후 포토 레지스트 위의 제2산화막을 습식 또는 건식 에치로 제거하고 포토 레지스트를 제거하는 단계(f)를 구비하는 것을 특징으로 하는 반도체 메모리 소자의 캐패시터 제조방법.A method for manufacturing a capacitor of a semiconductor memory device, the method comprising: forming a field oxide film on a silicon substrate, forming a gate polysilicon, a cap oxide film, a first polysilicon, and a first oxide film (a), etching the gate, and forming a thin nitride film on the entire surface After the deposition, the nitride film is etched back and the first oxide film is removed on the first polysilicon (b). After the second oxide film is coated, a sidewall is formed and the third oxide film is coated again. (C) defining a mask, depositing node polysilicon after etching the buried contact, and defining (d), defining the node mask, etching the node polysilicon, removing the node mask, and then coating the photoresist. Step (e), the photoresist is etched back until the first polysilicon on the cap oxide film comes out, and then the second oxide film on the photoresist is wet or dry etched. And removing the photoresist and removing the photoresist. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910016078A 1991-09-16 1991-09-16 Method of making capacitor of semiconductor memory device KR940001255B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910016078A KR940001255B1 (en) 1991-09-16 1991-09-16 Method of making capacitor of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910016078A KR940001255B1 (en) 1991-09-16 1991-09-16 Method of making capacitor of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR930006915A true KR930006915A (en) 1993-04-22
KR940001255B1 KR940001255B1 (en) 1994-02-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910016078A KR940001255B1 (en) 1991-09-16 1991-09-16 Method of making capacitor of semiconductor memory device

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KR940001255B1 (en) 1994-02-18

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