KR930005737B1 - Method of for fabricating semiconductor memory cell - Google Patents
Method of for fabricating semiconductor memory cell Download PDFInfo
- Publication number
- KR930005737B1 KR930005737B1 KR1019900018364A KR900018364A KR930005737B1 KR 930005737 B1 KR930005737 B1 KR 930005737B1 KR 1019900018364 A KR1019900018364 A KR 1019900018364A KR 900018364 A KR900018364 A KR 900018364A KR 930005737 B1 KR930005737 B1 KR 930005737B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- oxide film
- forming
- gate
- patterning
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 4
- 238000000034 method Methods 0.000 title abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 238000003860 storage Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 종래의 공정 단면도.1 is a cross-sectional view of a conventional process.
제2도는 본 발명의 공정 단면도.2 is a cross-sectional view of the process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 필드산화막1 substrate 2 field oxide film
3 : 게이트산화막 4 : 게이트 폴리실리콘3: gate oxide film 4: gate polysilicon
5 : 제1산화막 6 : 소오스/드레인 영역5: first oxide film 6: source / drain region
7 : 스토리지 노드 폴리실리콘 8 : 커패시터 절연막7: storage node polysilicon 8: capacitor insulating film
9 : 플레이트 폴리실리콘 10 : 제2산화막9: plate polysilicon 10: second oxide film
11 : 제3산화막 12 : 포토레지스터11: third oxide film 12: photoresist
13 : 폴리실리콘 14 : 절연막13: polysilicon 14: insulating film
15 : 비트라인15: bitline
본 발명은 반도체 메모리 셀 제조방법에 관한 것으로, 특히 게이트 폴리실리콘과 플레이트 폴리실리콘을 동시에 패터닝하고 자기 정합(Self-Align)법으로 콘택을 형성하여 오버레이어큐러시(Overlay Accuracy)를 향상시키기에 적당하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory cell, and in particular, to pattern overlay gate polysilicon and plate polysilicon at the same time and to form a contact by a self-aligning method to improve overlay accuracy. I did it.
종래의 메모리 셀 제조방법은 제1a도와같이 통상의 방법으로 기판(20)에 트랜지스터와 필드산화막(21)을 형성하고 산화막(22)을 성장시킨 후 마스킹 공정에 의해 산화막(22)을 에치하여 매몰콘택을 형성한다.In the conventional memory cell manufacturing method, as shown in FIG. 1A, the transistor and the field oxide film 21 are formed on the substrate 20 in the usual manner, the oxide film 22 is grown, and the oxide film 22 is etched and buried by a masking process. Form a contact.
그리고 (B)와같이 스토리지 노드 폴리실리콘(23), 커패시터 절연막(24), 플레이트 폴리실리콘(25)을 차례로 형성하고 패터닝하여 커패시터를 형성한다.As shown in (B), the storage node polysilicon 23, the capacitor insulating film 24, and the plate polysilicon 25 are sequentially formed and patterned to form a capacitor.
다음에 (C)와 같이 BPSG등의 절연막(26)을 증착하고 콘택 에치한 후 비트라인(27)을 형성한다.Next, as shown in (C), an insulating film 26 such as BPSG is deposited and contact etched to form a bit line 27.
그러나, 상기와같은 종래기술에 있어서는 소자의 고집적화에 따라 최소 설계 선폭이 줄어들어 비트라인(27) 콘택과 게이트 혹은 플레이트 폴리실리콘(25) 사이의 간격을 전면에 필요한 일정한 두께이상(≥1000Å) 유지하기가 어렵다.However, in the prior art as described above, the minimum design line width is reduced according to the high integration of the device, so that the gap between the bit line 27 contact and the gate or plate polysilicon 25 is maintained at a predetermined thickness or more (≥ 1000 ms) on the front surface. Is difficult.
따라서, 본 발명은 이와같은 종래의 결점을 해결하기 위한 것으로, 게이트 폴리실리콘과 플레이트 폴리실리콘을 동시에 패터닝하고 이에 비트라인 콘택을 자기 정합으로 형성하여 집적도를 향상시킴과 아울러 공정을 단순화시키고자 하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned drawbacks, and to simultaneously pattern the gate polysilicon and the plate polysilicon and form a bitline contact with self-alignment to improve the degree of integration and simplify the process. There is a purpose.
이와같은 목적을 달성하기 위한 본 발명은 기판위에 필드산화막, 게이트 산화막, 게이트 폴리실리콘을 차례로 형성하고 패터닝하여 이온주입으로 소오스/드레인 영역 형성후 제1산화막을 성장시켜 선택적 식각하므로 매몰 콘택을 형성하는 공정과, 스토리지 노드 폴리실리콘 형성후 패터닝하고 커패시터 절연막을 형성하는 공정과, 플레이트 폴리실리콘과 제2산화막을 형성하고 이방성 건식식각으로 플레이트 폴리실리콘 게이트 폴리 실리콘을 동시에 패터닝하는 공정과, 제3산화막을 형성하고 이방성 건식식각으로 콘택 측벽에 산화막을 남기는 공정과, 포토레지스트를 마스크로하여 플레이트 폴리실리콘 위의 제2산화막을 부분적으로 식각하는 공정과, 도우핑된 폴리실리콘을 형성하고 패터닝하여 폴리실리콘 플러그를 형성하는 공정과, 절연막을 형성하고 콘택 에치한 후 비트라인을 형성하는 공정을 차례로 실시하여서 이루어짐을 특징으로 한다.In order to achieve the above object, the present invention forms a buried contact because a field oxide film, a gate oxide film, and a gate polysilicon are sequentially formed on a substrate and patterned to form a source / drain region by ion implantation, followed by growing a first oxide film to selectively etch. A process of forming a polysilicon layer and a second oxide film, patterning the plate polysilicon gate polysilicon at the same time by anisotropic dry etching, and patterning the third oxide film. Forming and leaving an oxide film on the contact sidewall by anisotropic dry etching; partially etching the second oxide film on the plate polysilicon using photoresist as a mask; forming and patterning doped polysilicon to form a polysilicon plug Forming an insulating film Sex and hayeoseo conducted sequentially a step of forming a bit line after a groping contact features a true.
이하에서 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상술하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.
먼저 (A)와 같이 기판(1)위에 필드산화막(2)과 게이트산화막(3), 게이트 폴리실리콘(4)을 차례로 형성하고 패터닝하여 이온주입으로 소오스/드레인영역(6)을 형성하며 그위에 제1산화막(5)을 형성하고 이 제1산화막(5)를 마스킹 공정으로 선택적으로 식각하여 매몰콘택을 형성한다.First, as shown in (A), a field oxide film 2, a gate oxide film 3, and a gate polysilicon 4 are sequentially formed and patterned on the substrate 1 to form a source / drain region 6 by ion implantation thereon. The first oxide film 5 is formed and the first oxide film 5 is selectively etched by a masking process to form a buried contact.
다음에 (B)와 같이 스토리지 노드 폴리실리콘(7)을 형성 후 패터닝하고 커패시터 절연막(8)을 형성한다.Next, as shown in (B), the storage node polysilicon 7 is formed and then patterned to form a capacitor insulating film 8.
이어서 (C)와 같이 플레이트 폴리실리콘(9)과 제2산화막(10)을 형성하고 이방성 건식식각으로 플레이트 폴리시릴콘(9)과 게이트 폴리실리콘(4)을 동시에 패터닝한다.Subsequently, the plate polysilicon 9 and the second oxide film 10 are formed as shown in (C), and the plate polysilicon 9 and the gate polysilicon 4 are simultaneously patterned by anisotropic dry etching.
그리고 (D)와 같이 제3 산화막(11)을 형성하고 이방성 건식식각으로 콘택 측벽에 제3 산화막(11)이 남게한다.As shown in (D), the third oxide film 11 is formed, and the third oxide film 11 is left on the contact sidewall by anisotropic dry etching.
이후, (E)와같이 포토레지스트(12)를 마스크로 이용하여 플레이트 폴리실리콘(9)위에 제2 산화막(10)을 부분적으로 식각 제거한다. 또한, (F)와 같이 도우핑된 폴리실리콘(13)을 형성하고 패터닝하여 폴리실리콘 플러그를 형성한다.Thereafter, as shown in (E), the second oxide film 10 is partially etched away on the plate polysilicon 9 using the photoresist 12 as a mask. In addition, as shown in (F), the doped polysilicon 13 is formed and patterned to form a polysilicon plug.
다음에 (G)와같이 절연막(14)을 형성하고 콘택에치한 후 비트라인(15)을 형성한다.Next, as shown in (G), the insulating film 14 is formed and contact etched to form a bit line 15.
상기와같은 본 발명에 의하면 게이트 폴리실리콘(4)과 플레이트 폴리실리콘(9)을 동시에 패터닝하고 여기에 비트라인(15) 콘택을 자기 정합으로 형성하므로 오버레이 어큐러시를 향상시킬 수 있으며, 비트라인(15) 콘택과 게이트, 플레이트 폴리실리콘(9)사이의 제1, 제2산화막(5)(10)두께가 일정두께 이상(≥1000Å)으로 유지되므로 집적도를 향상시킬 수 있을뿐만 아니라 마스크 단계가 줄어들어 공정단순화를 얻을 수 있다.According to the present invention as described above, the gate polysilicon 4 and the plate polysilicon 9 are patterned at the same time, and the bit line 15 contacts are formed by self-alignment, thereby improving overlay acuity. 15) Since the thicknesses of the first and second oxide films 5 and 10 between the contact, gate, and plate polysilicon 9 are maintained at a predetermined thickness or more (≥1000 microseconds), not only the density can be improved but also the mask stage is reduced. Process simplification can be obtained.
또한, 비트라인(15) 형성시 절연막(14)의 단차가 낮아 스텝커버 리지를 향상시킬 수 있는 장점이 있다.In addition, when the bit line 15 is formed, the step difference of the insulating layer 14 is low, thereby improving the step coverage.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900018364A KR930005737B1 (en) | 1990-11-13 | 1990-11-13 | Method of for fabricating semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900018364A KR930005737B1 (en) | 1990-11-13 | 1990-11-13 | Method of for fabricating semiconductor memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920010898A KR920010898A (en) | 1992-06-27 |
| KR930005737B1 true KR930005737B1 (en) | 1993-06-24 |
Family
ID=19305988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900018364A KR930005737B1 (en) | 1990-11-13 | 1990-11-13 | Method of for fabricating semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930005737B1 (en) |
-
1990
- 1990-11-13 KR KR1019900018364A patent/KR930005737B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920010898A (en) | 1992-06-27 |
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