KR930003594A - Alarm display signal state detector of digital synchronous multiplexer - Google Patents

Alarm display signal state detector of digital synchronous multiplexer Download PDF

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KR930003594A
KR930003594A KR1019910011811A KR910011811A KR930003594A KR 930003594 A KR930003594 A KR 930003594A KR 1019910011811 A KR1019910011811 A KR 1019910011811A KR 910011811 A KR910011811 A KR 910011811A KR 930003594 A KR930003594 A KR 930003594A
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input
signal
clock
clear
alarm display
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KR950001926B1 (en
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고제수
김재근
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경상현
재단법인 한국전자통신연구소
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

내용 없음.No content.

Description

디지틀 동기 다중화기의 경보표시신호 상태 검출기Alarm display signal state detector of digital synchronous multiplexer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 동기식 다중신호 전송프레임의 구조도,1 is a structural diagram of a synchronous multi-signal transmission frame,

제2도는 본 발명에 의한 경보표시신호 상태 검출기의 구성도.2 is a block diagram of an alarm display signal state detector according to the present invention.

Claims (2)

동기 전송시스팀의 동기 다중화기에 수신 다중화 신호의 경보표시신호의 상태를 검출하기 위한 경보표시신호 상태 검출기에 있어서; 포인터 워드신호가 입력단으로 입력되고 포인터 클럭(PK)을 클럭 입력으로 하는 제1래치수단(1), 상기 제1래치수단(1)의 출력단에 입력단이 연결된 제1논리곱 수단(2), 클리어신호(/CL)와 제어신호(/ST)를 입력으로 하는 제2논리곱수단(12), 상기 클리어신호(/CL)가 반전된 반전 클리어 신호(CL)와 제1논리곱수단(2)에 입력단이 연결된 제1부정논리합수단(5), 상기 제1논리곱수단(2)의 출력과 포인터 클럭(PK)과 클리어신호(/CL)를 입력으로 하는 지연수단(13), 상기 지연수단(13)의 출력단과 상기 제1 부정논리합수단(5)의 출력단에 입력단이 연결된 제2부정논리합수단(6), 상기 제2논리곱수단(12)의 출력을 데이타 입력으로 하고 제어신호(SK)를 반전시켜 클럭 입력으로 하고 상기 클리어신호(/CL)를 클리어 입력으로 하는 제1 D플립플롭(8), 및 상기 제2논리곱수단(12)의 반전출력과 제2 부정논리합수단(6)의 출력을 입력으로 하고 상기 제어 신호(SK)를 클럭 입력으로 하고 상기 제1 D플립플롭(8)의 출력을 클리어 입력으로 하는 제2래치수단(7)으로 구성되는 것을 특징으로 하는 경보표시신호 상태 검출기.An alarm display signal state detector for detecting a state of an alarm display signal of a received multiplex signal to a synchronous multiplexer of a synchronous transmission system; A first latch means (1) for inputting a pointer word signal to an input terminal and a pointer clock (PK) as a clock input; Second logical multiplication means (12) for inputting signal (CL) and control signal (/ ST), inverted clear signal (CL) and first logical multiplication means (2) in which the clear signal (/ CL) is inverted A first negative logic summation means 5 connected to an input terminal thereof, a delay means 13 for inputting an output of the first logical multiplication means 2, a pointer clock PK, and a clear signal / CL, and the delay means. The second negative logic summation means 6 and the second logical multiplication means 12, whose inputs are connected to the output end of 13 and the output end of the first negative logic summation means 5, and the control signal SK Inverting the first D flip-flop 8 and the second logical multiplication means 12 which inverts the clock signal input and the clear signal / CL as the clear input. And the second latch means 7 which inputs the output of the second negative logic means 6 as the input, the control signal SK as the clock input, and the output of the first D flip-flop 8 as the clear input. Alarm display signal state detector, characterized in that configured. 제1항에 있어서, 상기 지연수단(13)은 상기 제1논리곱수단(2)의 출력을 데이타 입력으로 하고 포인터 클럭(PK)을 클럭 입력으로 하고 상기 클리어신호(/CL)를 프리세트 입력으로 하는 제2 D플립플로(3), 및 상기 제2 D플립플롭(3)의 출력을 데이타 입력으로 하고 포인터 클럭(PK)를 클럭 입력으로 하고 상기 클리어 신호(/CL)를 클리어 입력으로 하는 제3 D플립플롭(4)으로 구성된 것을 특징으로 하는 경보표시신호 상태 검출기.2. The delay means (13) according to claim 1, wherein the delay means (13) uses the output of the first logical product (2) as a data input, the pointer clock (PK) as a clock input, and the clear signal (/ CL) as a preset input. The second D flip-flop 3 and the output of the second D flip-flop 3 are data inputs, the pointer clock PK is a clock input, and the clear signal / CL is a clear input. Alarm display signal state detector, characterized in that consisting of a third D flip-flop (4). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910011811A 1991-07-11 1991-07-11 Alarm indication signal state detector in the digital synchronous multiplexer Expired - Fee Related KR950001926B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011811A KR950001926B1 (en) 1991-07-11 1991-07-11 Alarm indication signal state detector in the digital synchronous multiplexer

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Application Number Priority Date Filing Date Title
KR1019910011811A KR950001926B1 (en) 1991-07-11 1991-07-11 Alarm indication signal state detector in the digital synchronous multiplexer

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KR930003594A true KR930003594A (en) 1993-02-24
KR950001926B1 KR950001926B1 (en) 1995-03-06

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