KR970013741A - Digital Data Thermal Level Detector - Google Patents

Digital Data Thermal Level Detector Download PDF

Info

Publication number
KR970013741A
KR970013741A KR1019950026613A KR19950026613A KR970013741A KR 970013741 A KR970013741 A KR 970013741A KR 1019950026613 A KR1019950026613 A KR 1019950026613A KR 19950026613 A KR19950026613 A KR 19950026613A KR 970013741 A KR970013741 A KR 970013741A
Authority
KR
South Korea
Prior art keywords
flop
counter
output
output signal
result
Prior art date
Application number
KR1019950026613A
Other languages
Korean (ko)
Other versions
KR100217156B1 (en
Inventor
조현주
Original Assignee
정장호
엘지정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정장호, 엘지정보통신 주식회사 filed Critical 정장호
Priority to KR1019950026613A priority Critical patent/KR100217156B1/en
Publication of KR970013741A publication Critical patent/KR970013741A/en
Application granted granted Critical
Publication of KR100217156B1 publication Critical patent/KR100217156B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 입력되는 데이타 열이 16비트일 경우 하이 또는 로우 레벨을 검출하기에 적당하도록 한 디지탈 데이타열 레벨 검출장치에 관한 것이다. 이러한 본 발명은 입력되는 클럭을 위상 반전시키는 인버터게이트와, 인버터게이트에서 출력되는 클럭으로 입력 데이타를 래치시키는 제1디플립플롭과, 제1디플립플롭의 출력신호가 로우상태이면 동작하여 입력값을 카운트하고 그 결과값을 출력하는 제1카운터와, 제1디플립플롭의 출력신호가 하이상태이면 동작하여 입력값을 카운트하고 그 결과치를 출력하는 제2카운터와, 제1카운터의 출력을 클럭으로하여 반전 출력신호를 래치시켜 그 결과치를 로우레벨 검출신호로 출력하는 제2디플립플롭과, 제2카운터의 출력을 클럭으로하여 반전출력신호를 래치시켜 그 결과치를 하이레벨 검출신호로 출력하는 제3디플립플롭으로 이루어진다.The present invention relates to a digital data string level detecting apparatus suitable for detecting a high or low level when an input data string is 16 bits. The present invention operates when the inverter gate phase-inverts the input clock, the first deflip-flop latching the input data with the clock output from the inverter gate, and the output signal of the first deflip-flop is low. Counts the first counter and outputs the result, a second counter that operates when the output signal of the first flip-flop is high, counts the input value and outputs the result, and clocks the output of the first counter. Second flip-flop that latches the inverted output signal and outputs the result as the low level detection signal, and latches the inverted output signal with the output of the second counter as a clock to output the result as the high level detection signal. It consists of a 3rd flip-flop.

Description

디지탈 데이타 열 레벨 검출장치Digital Data Thermal Level Detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 디지탈 데이타 열 레벨 검출장치 구성도.2 is a block diagram of a digital data column level detector according to the present invention.

Claims (1)

입력되는 클럭을 위상 반전시키는 인버터게이트와, 상기 인버터게이트에서 출력되는 클럭으로 입력 데이타를 래치시키는 제1디플립플롭과, 상기 제1디플립플롭의 출력신호가 로우상태이면 동작하여 입력값을 카운트하고 그 결과값을 출력하는 제1카운터와, 상기 제1디플립플롭의 출력신호가 하이상태이면 동작하여 입력값을 카운트하고 그 결과치를 출력하는 제2카운터와, 상기 제1카운터의 출력을 클럭으로하여 반전 출력신호를 래치시켜 그 결과치를 로우레벨 검출신호로 출력하는 제2디플립플롭과, 상기 제2카운터의 출력을 클럭으로하여 반전출력신호를 래치시켜 그 결과치를 하이레벨 검출신호로 출력하는 제3디플립플롭으로 구성된 것을 특징으로 하는 디지탈 데이타 레벨 검출장치.An inverter gate for inverting a phase of an input clock, a first deflip flop for latching input data with a clock output from the inverter gate, and an output signal of the first deflip flop is operated to count an input value A first counter that outputs the resultant value, a second counter that operates when the output signal of the first deflip-flop is high, counts an input value, and outputs the resultant value, and clocks the output of the first counter. Second flip-flop for latching the inverted output signal and outputting the result as the low level detection signal; and latching the inverted output signal with the output of the second counter as a clock and outputting the result as the high level detection signal. And a third dip flip-flop. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950026613A 1995-08-25 1995-08-25 Level detector of digital data row KR100217156B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950026613A KR100217156B1 (en) 1995-08-25 1995-08-25 Level detector of digital data row

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950026613A KR100217156B1 (en) 1995-08-25 1995-08-25 Level detector of digital data row

Publications (2)

Publication Number Publication Date
KR970013741A true KR970013741A (en) 1997-03-29
KR100217156B1 KR100217156B1 (en) 1999-09-01

Family

ID=19424513

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950026613A KR100217156B1 (en) 1995-08-25 1995-08-25 Level detector of digital data row

Country Status (1)

Country Link
KR (1) KR100217156B1 (en)

Also Published As

Publication number Publication date
KR100217156B1 (en) 1999-09-01

Similar Documents

Publication Publication Date Title
KR880008563A (en) Synchronous circuit
KR940017121A (en) Variable length code decoding device
KR970013741A (en) Digital Data Thermal Level Detector
KR900015474A (en) Digital data expansion method and data expansion circuit
KR870005392A (en) Master latch circuit
KR920017417A (en) DTMF signal detection device and method
KR930024337A (en) Frame Synchronization Detection Method and Circuit for Demultiplexing Data Transmission System
KR920014182A (en) Synchronous signal detection circuit
KR910015927A (en) Sequential "1" Detection Circuit
KR880005756A (en) Stabilization circuit using digital PL circuit of modem received data
KR950022339A (en) Delay-free channel alignment circuit
KR930011461A (en) ES detection circuit of transmission system
KR950016272A (en) Clock synchronization circuit
KR920011119A (en) CPC detection circuit
KR950015102A (en) Serial I / O Interface Circuit
KR890001310A (en) Digital data transmission circuit by PWM coding / decoding
KR910012922A (en) Automatic state detection circuit of microprocessor control system
KR930003594A (en) Alarm display signal state detector of digital synchronous multiplexer
KR970012702A (en) Asynchronous Semiconductor Memory Device Using Synchronous Semiconductor Memory Device
KR890013914A (en) Channel assignment circuit of digital exchange
KR950022089A (en) Synchronous signal detection circuit
KR960027396A (en) Alarm generator of high speed transmission system
KR920011121A (en) Digital alarm display signal detection circuit
KR870002546A (en) Synchronization Detection Method of Digital Audio Equipment
KR970051280A (en) Clock Sampling Unit for Synchronous Memory

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030219

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee