KR930022737A - Method and apparatus for decoding digital signal - Google Patents

Method and apparatus for decoding digital signal Download PDF

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KR930022737A
KR930022737A KR1019920006857A KR920006857A KR930022737A KR 930022737 A KR930022737 A KR 930022737A KR 1019920006857 A KR1019920006857 A KR 1019920006857A KR 920006857 A KR920006857 A KR 920006857A KR 930022737 A KR930022737 A KR 930022737A
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sampling
predetermined
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reference value
value
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KR1019920006857A
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KR950005814B1 (en
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이성모
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이민화
주식회사 메디슨
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 소정의 주기로 샘플링된 데이타를 디코딩하기 위한 방법 및 장치에 관한 것으로 1도트만큼 지연주기를 갖는 2개의 샘플링값을 연속적으로 산출하고 이 2개의 샘플링값과 소정의 비교기준값을 비교하여, 비교기준값이 2개의 샘플링값의 사이에 존재하거나, 비교기준값이 2개 샘플링값 중의 하나 또는 모두와 동일한 경우 일정크기의 신호를 출력하는 디코딩방법 및 장치이다. 본 발명에 의한 디코딩방식은 샘플링된 데이타를 화면에 수평 또는 수직방향으로 맵핑되도록 디코딩할 수 있으며, 종래보다 간단한 하드웨어로서 디코딩을 수행할 수 있다.The present invention relates to a method and apparatus for decoding data sampled at a predetermined period, and continuously calculates two sampling values having a delay period by one dot, compares these two sampling values with a predetermined reference value, and compares them. A decoding method and apparatus for outputting a signal having a predetermined size when a reference value exists between two sampling values or when a comparison reference value is equal to one or both of two sampling values. The decoding method according to the present invention can decode the sampled data to be mapped in a horizontal or vertical direction on the screen, and can perform decoding as hardware simpler than the prior art.

Description

디지탈신호의 디코딩방법 및 장치Method and apparatus for decoding digital signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 디코딩장치의 일실시예를 나타내는 블럭도.1 is a block diagram showing an embodiment of a decoding apparatus according to the present invention.

제2도는 제1도의 실시예에서 디스플레이되는 화면을 나타내는 개략도.2 is a schematic diagram showing a screen displayed in the embodiment of FIG.

제3도는 본 발명에 의한 디코딩장치의 다른 일실시예를 나타내는 블럭도.3 is a block diagram showing another embodiment of a decoding apparatus according to the present invention.

Claims (16)

소정주기로 샘플링된 데이타를 디코딩하기 위한 방법에 있어서, 샘플링데이타를 공급받아 임의의 샘플링값과 이 보다 소정주기 이전의 샘플링값을 산출하는 단계와; 일정구간내에서 소정주기의 비교기준값을 순차적으로 발생하는 단계와; 상기 샘플링값 산출단계에서 얻어진 2개의 샘플링값을 상기 비교기준값과 각각 비교하는 단계와; 상기 비교단게에서 얻어진 결과값들에 대해 소정의 논리연산을 수행하는 단계와; 상기 논리연산결과를 소정 클럭에 맞춰 출력하는 단계를 포함하는 디코딩방법.CLAIMS 1. A method for decoding data sampled at a predetermined period, comprising: receiving sampling data to calculate an arbitrary sampling value and a sampling value before the predetermined period; Sequentially generating comparison reference values of a predetermined period within a predetermined period; Comparing the two sampling values obtained in the sampling value calculating step with the comparison reference value, respectively; Performing a predetermined logical operation on the result values obtained in the comparison step; And outputting the logical operation result in accordance with a predetermined clock. 제1항에 있어서, 상기 샘플링값 산출단계는 지연주기로 도트클럭을 사용하여 하나의 샘플링값이 다른 샘플링값보다 1도트클럭만큼 지연되는 것을 특징으로 하는 디코딩방법.The decoding method according to claim 1, wherein the sampling value calculating step uses one dot clock as a delay period to delay one sampling value by one dot clock than another sampling value. 제1항에 있어서, 상기 비교기준값은 소정의 수직윈도우구간내에서 수평동기신호를 카운팅하여 얻어지는 것을 특징으로 하는 디코딩 방법.The decoding method of claim 1, wherein the comparison reference value is obtained by counting a horizontal synchronization signal within a predetermined vertical window section. 제1항에 있어서, 상기 비교기준값은 소정의 수직윈도우구간내에서 도트클럭을 카운팅하여 얻어지는 것을 특징으로 하는 디코딩 방법.The decoding method according to claim 1, wherein the comparison reference value is obtained by counting a dot clock within a predetermined vertical window section. 제1항에 있어서, 상기 논리연산단게는 상기 비교단계의 결과에서, 비교기준값이 2개의 샘플링값의 사이에 존재하거나, 비교기준값이 2개 샘플링값 중의 하나 또는 모두와 동일한 경우 일정크기의 데이타를 출력하는 것을 특징으로 하는 디코딩방법.The method of claim 1, wherein the logic operation step is configured to generate data of a predetermined size when the comparison reference value exists between two sampling values, or when the comparison reference value is equal to one or both of the two sampling values. Decoding method characterized in that the output. 제1항 는 제5항에 있어서, 상기 논리연산단계는 소정의 수직윈도우 및 수평윈도우구간내에서 수행되는 것을 특징으로 하는 디코딩방법.The decoding method according to claim 5, wherein the logic operation is performed within a predetermined vertical window and a horizontal window section. 제1항에 있어서, 상기 논리연산결과의 출력단계는 상기 논리연산결과를 도트클럭에 맞춰 1비트씩 출력하는 것을 특징으로 하는 디코딩방법.The decoding method according to claim 1, wherein the outputting of the logical operation result outputs the logical operation result one bit in accordance with a dot clock. 소정주기로 샘플링된 데이타를 디코딩하기 위한 장치에 있어서, 샘플링데이타를 공급받아 임의의 샘플링값과 이 보다 소정주기 이전의 샘플링값을 출력하는 수단과; 일정구간내에서 소정주기의 비교기준값을 순차적으로 발생하는 수단과; 상기 샘플링값 출력수단에서 얻어진 2개의 샘플링값을 상기 비교기준값과 각각 비교하는 수단과; 상기 비교수단의 출력값들에 대해 소정의 논리연산을 수행하는 수단과; 상기 논리연산결과를 소정클럭에 맞춰 출력하는 수단을 포함하는 디코딩장치.An apparatus for decoding data sampled at a predetermined period, comprising: means for receiving sampling data and outputting a random sampling value and a sampling value before the predetermined period; Means for sequentially generating a comparison reference value of a predetermined period within a predetermined period; Means for comparing two sampling values obtained by said sampling value output means with said comparison reference value, respectively; Means for performing a predetermined logical operation on the output values of the comparing means; And means for outputting the logical operation result in accordance with a predetermined clock. 제8항에 있어서, 상기 샘플링값 출력수단은 샘플링데이타를 공급받아 소정의 도트클럭에 맞춰 샘플링값을 출력하는 제1래치와; 상기 제1래치에서 출력되는 샘플링값을 공급받아 상기 도트클럭에 맞춰 샘플링값을 출력하는 제2래치를 포함하는 것을 특징으로 하는 디코딩장치.9. The apparatus of claim 8, wherein the sampling value output means comprises: a first latch receiving sampling data and outputting a sampling value in accordance with a predetermined dot clock; And a second latch receiving the sampling value output from the first latch and outputting a sampling value in accordance with the dot clock. 제8항에 있어서, 상기 비교기준값 발생수단은 소정의 수직윈도우신호에 의해 설정되는 소정구간내에서 수평동기신호를 카운팅하여 얻어지는 값을 비교기준값으로 발생하는 카운터인 것을 특징으로 하는 디코딩장치.9. The decoding apparatus according to claim 8, wherein the comparison reference value generating means is a counter that generates a value obtained by counting a horizontal synchronization signal within a predetermined section set by a predetermined vertical window signal as a comparison reference value. 제8항에 있어서, 상기 비교기준값 발생수단은 소정의 수평윈도우신호에 의해 설정되는 소정구간내에서 도트클럭을 카운팅하여 얻어지는 값을 비교기준값으로 발생하는 카운터인 것을 특징으로 하는 디코딩장치.9. The decoding apparatus according to claim 8, wherein the comparison reference value generating means is a counter that generates a value obtained by counting a dot clock within a predetermined section set by a predetermined horizontal window signal as a comparison reference value. 제8항에 있어서, 상기 비교수단은 상기 제1래치에서 출력되는 샘플링값과 상기 카운터에서 출력되는 비교기준값을 비교하는 제1비교기와; 상기 제2래치에서 출력되는 샘플링값과 상기 카운터에서 출력되는 비교기준값을 비교하는 제2비교기를 포함하는 것을 특징으로 하는 디코딩장치.9. The apparatus of claim 8, wherein the comparing means comprises: a first comparator for comparing a sampling value output from the first latch and a comparison reference value output from the counter; And a second comparator for comparing the sampling value output from the second latch and the comparison reference value output from the counter. 제8항에 있어서, 상기 논리연산수단은 상기 비교수단의 출력을 공급받아, 비교기준값이 2개 샘플링값의 사이에 존재하거나, 비교기준값이 2개 샘플링값 중의 하나 또는 모두와 동일한 경우 일정크기의 데이타를 출력하는 논리소자인 것을 특징으로 하는 디코딩장치.10. The method of claim 8, wherein the logic operation means receives the output of the comparison means, and if the comparison reference value exists between two sampling values, or the comparison reference value is equal to one or both of the two sampling values, A decoding device, characterized in that the logic device for outputting data. 제8항 는 제3항에 있어서, 상기 논리연산수단은 소정의 수직윈도우신호 및 수평윈도우신호에 의해 설정되는 구간내에서 논리연산을 수행하는 것을 특징으로 하는 디코딩장치.The decoding apparatus according to claim 8, wherein the logical operation means performs a logical operation within a section set by a predetermined vertical window signal and a horizontal window signal. 제8항에 있어서, 상기 논리연산결과의 출력수단은 상기 논리연산수단에서 공급되는 출력데이타를 도트클럭에 맞춰 1비트씩 출력하는 플립플롭인 것을 특징으로 하는 디코딩장치.9. The decoding apparatus according to claim 8, wherein the outputting means of the logical operation result is a flip-flop which outputs the output data supplied from the logic operation means one bit in accordance with a dot clock. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920006857A 1992-04-23 1992-04-23 Method and apparatus for decoding digital signal for display KR950005814B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112653924A (en) * 2020-12-15 2021-04-13 上海安路信息科技有限公司 HDMI receiving method and device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112653924A (en) * 2020-12-15 2021-04-13 上海安路信息科技有限公司 HDMI receiving method and device

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