KR930022737A - Method and apparatus for decoding digital signal - Google Patents

Abstract

The present invention relates to a method and apparatus for decoding data sampled at a predetermined period, and continuously calculates two sampling values having a delay period by one dot, compares these two sampling values with a predetermined reference value, and compares them. A decoding method and apparatus for outputting a signal having a predetermined size when a reference value exists between two sampling values or when a comparison reference value is equal to one or both of two sampling values. The decoding method according to the present invention can decode the sampled data to be mapped in a horizontal or vertical direction on the screen, and can perform decoding as hardware simpler than the prior art.

Description

Method and apparatus for decoding digital signal

Since this is an open matter, no full text was included.

1 is a block diagram showing an embodiment of a decoding apparatus according to the present invention.

2 is a schematic diagram showing a screen displayed in the embodiment of FIG.

3 is a block diagram showing another embodiment of a decoding apparatus according to the present invention.

Claims (16)

CLAIMS 1. A method for decoding data sampled at a predetermined period, comprising: receiving sampling data to calculate an arbitrary sampling value and a sampling value before the predetermined period; Sequentially generating comparison reference values of a predetermined period within a predetermined period; Comparing the two sampling values obtained in the sampling value calculating step with the comparison reference value, respectively; Performing a predetermined logical operation on the result values obtained in the comparison step; And outputting the logical operation result in accordance with a predetermined clock. The decoding method according to claim 1, wherein the sampling value calculating step uses one dot clock as a delay period to delay one sampling value by one dot clock than another sampling value. The decoding method of claim 1, wherein the comparison reference value is obtained by counting a horizontal synchronization signal within a predetermined vertical window section. The decoding method according to claim 1, wherein the comparison reference value is obtained by counting a dot clock within a predetermined vertical window section. The method of claim 1, wherein the logic operation step is configured to generate data of a predetermined size when the comparison reference value exists between two sampling values, or when the comparison reference value is equal to one or both of the two sampling values. Decoding method characterized in that the output. The decoding method according to claim 5, wherein the logic operation is performed within a predetermined vertical window and a horizontal window section. The decoding method according to claim 1, wherein the outputting of the logical operation result outputs the logical operation result one bit in accordance with a dot clock. An apparatus for decoding data sampled at a predetermined period, comprising: means for receiving sampling data and outputting a random sampling value and a sampling value before the predetermined period; Means for sequentially generating a comparison reference value of a predetermined period within a predetermined period; Means for comparing two sampling values obtained by said sampling value output means with said comparison reference value, respectively; Means for performing a predetermined logical operation on the output values of the comparing means; And means for outputting the logical operation result in accordance with a predetermined clock. 9. The apparatus of claim 8, wherein the sampling value output means comprises: a first latch receiving sampling data and outputting a sampling value in accordance with a predetermined dot clock; And a second latch receiving the sampling value output from the first latch and outputting a sampling value in accordance with the dot clock. 9. The decoding apparatus according to claim 8, wherein the comparison reference value generating means is a counter that generates a value obtained by counting a horizontal synchronization signal within a predetermined section set by a predetermined vertical window signal as a comparison reference value. 9. The decoding apparatus according to claim 8, wherein the comparison reference value generating means is a counter that generates a value obtained by counting a dot clock within a predetermined section set by a predetermined horizontal window signal as a comparison reference value. 9. The apparatus of claim 8, wherein the comparing means comprises: a first comparator for comparing a sampling value output from the first latch and a comparison reference value output from the counter; And a second comparator for comparing the sampling value output from the second latch and the comparison reference value output from the counter. 10. The method of claim 8, wherein the logic operation means receives the output of the comparison means, and if the comparison reference value exists between two sampling values, or the comparison reference value is equal to one or both of the two sampling values, A decoding device, characterized in that the logic device for outputting data. The decoding apparatus according to claim 8, wherein the logical operation means performs a logical operation within a section set by a predetermined vertical window signal and a horizontal window signal. 9. The decoding apparatus according to claim 8, wherein the outputting means of the logical operation result is a flip-flop which outputs the output data supplied from the logic operation means one bit in accordance with a dot clock. ※ Note: The disclosure is based on the initial application.