KR950004728A - Burst Gate Pulse Generator Circuit - Google Patents

Abstract

In the present invention, the burst gate pulse generator circuit is composed of a logic circuit in a VTR system that does not use a feedback pulse (FBP). Problems that are difficult to induce can be prevented, and the compactness can be achieved by simplifying the circuit.

Description

Burst Gate Pulse Generator Circuit

Since this is an open matter, no full text was included.

1 is a schematic block diagram of the present invention, and FIG. 2 is a detailed circuit diagram of the present invention.

Claims (6)

A burst gate pulse generation circuit having a horizontal synchronization signal and a reference clock as an input, wherein the reference clock is input to generate a pulse during a back porch section in which a burst signal exists among elements constituting a composite video signal. A burst gate pulse generator for generating a burst gate pulse having a predetermined width during the back porch period by counting a clock; A reset signal generator for providing a reset signal to the burst gate pulse generator by latching the horizontal sync signal and the delay signal by inputting the horizontal sync signal and a predetermined delay signal; And a delay signal generator for outputting a delay signal by delaying the first output signal by a predetermined time by inputting a predetermined first output signal from the reference clock and the burst gate pulse generator. Burst gate pulse generator circuit. The first pulse of claim 1, wherein the burst gate pulse generator generates a first pulse having a width obtained by dividing a width of a low level pulse of the horizontal synchronization signal by four by counting a pulse of the reference clock with the reference clock as an input. First pulse generating means for generating; By counting the first pulse with the first pulse as an input, a second pulse is generated which is twice the width of the low level pulse of the horizontal synchronization signal, and the high level pulse of the second pulse is the horizontal synchronization signal. The first output signal and the high level pulse of the second pulse delayed by four times the period of the first pulse from the falling edge of the low level pulse of the first pulse from the falling edge of the low level pulse of the horizontal synchronization signal. A second pulse generating means for providing a second output signal delayed by twice the period of; and the first output signal and the second output signal for outputting the burst gate pulse by inputting the first output signal and the second output signal. 2. A burst gate pulse generation circuit comprising a logic comparing means for logically comparing two output signals. 3. The method of claim 2, wherein the first pulse generating means is a first counting means for counting the reference clock as a clock signal and the first reset signal as a reset signal to have a period of the first pulse. Burst gate pulse generator circuit. 3. The method of claim 2, wherein the second pulse generating means is a second counting means for counting the first pulse as a clock signal and the second reset signal as a reset signal to have a period of the second pulse. A burst gate pulse generator circuit. The method of claim 1, wherein the reset signal generation unit receives the horizontal synchronization signal and the delay signal as inputs and latches the horizontal synchronization signal and the delay signal until the falling edge of the delay signal is generated from the falling edge of the horizontal synchronization signal. Latch means for generating a latch signal for indicating a; And a comparison signal for generating a comparison signal for negatively multiplying the delay signal to generate the second reset signal by negatively multiplying the latch signal and the second output signal using the latch signal and the second output signal as inputs. A burst gate pulse generating circuit comprising a generating means. 2. The apparatus of claim 1, wherein the delay signal generation unit comprises: delay signal clock generation means for generating a delay signal generation clock that is four times the reference clock pulse width by counting the reference clock as an input of the reference clock; Delay means for outputting the delayed signal generation clock as a clock signal and delaying the first output signal by half of the delayed signal generation clock period; And a negative logic to generate the delayed signal by inputting an output signal of the delay means and an inverted signal of the first output signal as negative inputs of the output signal of the delay means and the inverted signal of the first output signal. A burst gate pulse generator circuit comprising a gate. ※ Note: The disclosure is based on the initial application.