KR930002816B1 - Manufacture of lead frame - Google Patents

Manufacture of lead frame Download PDF

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Publication number
KR930002816B1
KR930002816B1 KR1019890017849A KR890017849A KR930002816B1 KR 930002816 B1 KR930002816 B1 KR 930002816B1 KR 1019890017849 A KR1019890017849 A KR 1019890017849A KR 890017849 A KR890017849 A KR 890017849A KR 930002816 B1 KR930002816 B1 KR 930002816B1
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South Korea
Prior art keywords
plating
lead
circuit pattern
lead frame
dam bar
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KR1019890017849A
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Korean (ko)
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KR900010984A (en
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미쓰하루 시미즈
미쓰히로 비야자와
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신고오 덴기 고오교오 가부시끼가이샤
이노우에 사다오
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음.No content.

Description

리드프레임의 가공방법Lead frame processing method

제 1 도는 제조할 리드프레임의 일예를 나타낸 설명도.1 is an explanatory diagram showing an example of a lead frame to be manufactured.

제 2 도는 댐바 안쪽의 미가공부분을 나타낸 설명도.2 is an explanatory diagram showing the unprocessed portion inside the dam bar.

제 3 도는 댐바로의 연결부를 폭좁게 형성한 상태의 설명도.3 is an explanatory diagram of a state in which the connecting portion to the dam bar is narrowly formed.

제 4 도는 종래예에 있어서의 타이바제거시의 절단선의 불일치의 상태를 나타낸 설명도.4 is an explanatory diagram showing a state of inconsistency of a cutting line when removing a tie bar in a conventional example.

본 발명은 댐바근방에 까지 리드측단면에 부분도금피막의 피착형성됨을 방지할 수 있는 리드프레임의 가공방법에 관한 것이다. 반도체장치용 리드프레임에는 와이어 본딩성을 향싱시키기 위하여 내부리드 선단부에 은도금, 금도금등의 부분도금이 행해진것이 있다. 이 부분도금은 프레스가공이나 코인닝가공등에 의한 악영향을 방지하기 위하여 우선 회로패턴을 프레스가공, 에칭가공등에 의해서 형성하고 또 내부리드선단에 코인닝가공을 행한후에 필요한 도금영역에 행하는 것이 바람직하다.The present invention relates to a method for processing a lead frame that can prevent the deposition of the partial plating film on the lead side end surface near the dam bar. In the lead frame for semiconductor devices, in order to enhance the wire bonding property, partial plating such as silver plating or gold plating has been performed at the inner lead ends. In order to prevent adverse effects caused by press work, coining, etc., the partial plating is preferably performed by pressing, etching, or the like, and then subjected to coining processing on the inner lead end, and then to the required plating area.

상기와 같이 먼저 회로패턴을 형성하면 부분도금시 탄성이 있는 마스크를 사용했다하더라도 마스크에 의해서 리드간의 간극을 완전하게 메꿀 수 없고 도금액이 리드사이에 누출되어 도금영역외의 리드측면에 불필요한 도금피막이 형성된다. 특개소 60-260142호 공보에는 상기 문제점을 해소하기 위하여 도금영역 외연부에 해당되는 부위에 인접하는 리드간의 간극을 메꾸는 타이바를 설비한 리드프레임이 제공되어 있다. 이 타이바는 프레스가공등에 의해서 회로패턴과 일체로 동시에 형성하든지 회로패턴 형성후에 상기 간극을 별도 수지등으로 메꾸어 형성한다. 그러나, 상기 종래의 리드프레임에서는 그 가공상 다음과 같은 문제점이 있었다. 즉, 리드프레임을 프레스가공으로 형성하는 경우에 댐바로 부터 내부리드 선단까지의 가공에서 보면 댐바와 타이바의 사이 : 타이바와 내부리드 선단까지의 사이에 폰칭가공에 더하여 부분도금후에 타이바를 절단하기 위한 가공이 필요하게되므로 폰칭가공을 위한 폰치도 많이 필요하게 된다는 문제점이 있다. 또, 타이바는 내부리드가 가느다란 곳에 형성되므로 타이바 제거시에 절단선이 내부리드의 측단면에 일치되지 않는 소위 미스메치가 생기기 쉽고(제 4 도) 또 내부리드를 변형시키는 원인으로도 된다. 타이바를 수지등의 절연물로 형성하면 타이바의 제거는 불필요하게 되지만 수지등의 타이바형성공정이 새롭게 필요하게되어 역시 공정수가 많아지는 문제점이 있다. 또 부분도금이 특히 은도금일 경우에 반도체장치 본체(예를들면 수지 모울드부)에서 외측으로 노출되는 외부리드부의 측단면에 은도금 피막이 형성되어 있으면 마이그레이숀등의 문제가 생긴다.If the circuit pattern is first formed as described above, even if an elastic mask is used for partial plating, the gap between the leads cannot be completely filled by the mask, and the plating liquid leaks between the leads, thereby forming an unnecessary plating film on the side of the lead outside the plating area. . Japanese Patent Application Laid-Open No. 60-260142 provides a lead frame equipped with a tie bar that fills a gap between leads adjacent to a portion corresponding to an outer edge of a plating area in order to solve the above problem. The tie bar is formed integrally with the circuit pattern by press working or the like, or after the circuit pattern is formed, the gap is filled with a resin or the like. However, the conventional lead frame has the following problems in its processing. In other words, when the lead frame is formed by press working, in the process from the dam bar to the inner lead end, the tie bar is cut between the dam bar and the tie bar: between the tie bar and the inner lead end in addition to the phoning process. Since there is a need for processing, there is a problem in that a lot of phonches for phoning processing are required. In addition, since the tie bar is formed in a narrow inner lead, when the tie bar is removed, a so-called mismatch where the cutting line does not coincide with the side cross section of the inner lead is likely to occur (FIG. 4) and also causes deformation of the inner lead. do. If the tie bar is formed of an insulator such as a resin, the tie bar is not required to be removed, but a tie bar forming process such as resin is newly required, and thus there is a problem of increasing the number of steps. In the case where the partial plating is particularly silver plating, if a silver plating film is formed on the side end surface of the outer lead portion exposed outward from the semiconductor device body (for example, the resin mold portion), problems such as migration may occur.

본 발명의 목적은 부분도금이 은도금피막의 경우에도 마이그레이숀의 문제가 생기지 않고, 공정수를 줄일 수 있어 원가의 저감을 도모할 수 있는 리드프레임을 제공하는데 있다.It is an object of the present invention to provide a lead frame which can reduce the number of processes without the problem of migration even when the partial plating is a silver plated film.

상기 목적에 의한 본 발명은 외부리드간를 연결시키는 댐바를 갖고 적어도 내부리드간의 도금필요장소에 은도금, 금도금등의 부분도금이 행해지는 리드프레임의 가공방법에 있어서, 형성해야할 회로패턴중 반도체장치에 조립시에 반도체장치 본체내에서 또 상기 도금필요장소에 도달되지 않는 위치와 상기 댐바와의 사이의 회로패턴을 제외하고 적어도 상기 도금필요 장소가 되는 부분의 회로패턴의 적어도 측단면을 형성하는 가공을 행하고 그런후에 상기 도금필요장소에 소요부분도금을 행하고 다음에 남는 미가공 부분의 회로패턴을 형성하는 가공을 행하는 것을 특징으로 한다.In accordance with the above object, the present invention provides a method of processing a lead frame in which a partial bar such as silver plating or gold plating is performed at least at a place where plating is required between inner leads, and has a dam bar connecting the outer leads. Processing to form at least the side cross-section of the circuit pattern of at least the portion to be plated, except for the circuit pattern between the dam bar and the position which does not reach the place where plating is required in the semiconductor device body at the time of Then, the required partial plating is carried out at the place where the plating is required, and then the machining is performed to form a circuit pattern of the next unprocessed portion.

이하 본 발명의 양호한 실시예를 첨부도면에 의하여 상세히 설명한다. 제 1 도는 형성할 리드프레임의 일예를 나타낸 설명도이며 10은 내부리드, 12는 외부리드, 14는 댐바, 16은 스테이지부, 18은 스테이지 시포트바, 20은 레일부, 22는 가이드홀이다. 또 1점쇄선으로 나타낸 범위내가 도금필요 장소이다. 또 스테이지부 16위에 도금을 행하지 않을 경우가 있다. 또 2점쇄선의 범위내가 수지모울드 영역이다.Hereinafter, preferred embodiments of the present invention will be described in detail by the accompanying drawings. 1 is an explanatory view showing an example of a lead frame to be formed, 10 is an inner lead, 12 is an outer lead, 14 is a dam bar, 16 is a stage part, 18 is a stage seaport bar, 20 is a rail part, and 22 is a guide hole. In addition, plating is required within the range indicated by the dashed line. Further, plating may not be performed on the stage 16. In addition, the resin mold region is within the range of the dashed-dotted line.

본 발명에서는 우선 적어도 내부리드 10을 포함하는 도금필요장소가 되는 부위의 회로패턴을 프레스가공 또는 에칭가공에 의해서 형성시킨다. 이 경우에 제 2 도에 나타낸 바와같이 적어도 댐바 14의 내측이고 반도체장치(예를들면 수지 모울드형 반도체장치)로서 조립했을때에 반도체장치 본체(예를들면 수지모울드부)에서 외측으로 노출되게 되는 부위의 회로패턴의 형성은 행하지 않는다. 제 2 도의 예에서는 2점쇄선으로 나타낸 모울드라인 A가 상기 수지모울드영역의 경계전이지만 이 모울드라인 A보다도 외측에서 댐바 14와의 사이 및 모울드라인 A보다도 내측의 소정범위에 걸쳐서는 회로패턴의 형성을 행하지 않은 것이다. 또 이 부분의 회로패턴의 형성은 도그필요장소로의 부분도금후에 행한다. 또 도금필요장소라함은 엄밀하게는 내부리드에 와이어 본딩성을 향상시키기 위하여 부분도금을 행하는 부위를 말하고 통상은 안정성을 감안하여 상기 부위보다도 약간 넓은 범위에 걸쳐서 부분도금이 행해진다. 댐바 14보다도 외측의 외부리드 12의 회로패턴은 상기 내측의 회로패턴과 동시에 형성시켜도 좋으며, 또는 부분도금후에 형성시켜도 좁다.In the present invention, first, a circuit pattern of a part which becomes a plating required place including at least the inner lead 10 is formed by press working or etching processing. In this case, as shown in FIG. 2, at least the inside of the dam bar 14 and when assembled as a semiconductor device (e.g., a resin mold type semiconductor device) are exposed to the outside from the main body of the semiconductor device (e.g., a resin mold part). The circuit pattern of the site | part is not formed. In the example of FIG. 2, the mold line A shown by the dashed-dotted line is before the boundary of the resin mold region, but the circuit pattern is formed over the predetermined range between the dam bar 14 and the inside of the mold line A outside the mold line A. I did not do it. In addition, the circuit pattern of this part is formed after partial plating to the dog place. In addition, the place where plating is required refers strictly to a part to be partially plated to improve wire bonding property to the inner lead, and in general, partial plating is performed over a slightly wider range than the above part in view of stability. The circuit pattern of the outer lead 12 outside the dam bar 14 may be formed at the same time as the circuit pattern on the inner side, or may be formed after partial plating.

다음에 필요에 따라서 내부리드 12의 와이어 본딩 에어리어에 코인닝 가공을 행한다.Next, a coining process is performed to the wire bonding area of the inner lead 12 as needed.

다음에 도금필요장소에 통상과 같은 소요 부분도금을 행한다. 이 경우에 리드프레임의 이면측에서는 윗판(도시치 않음)을 대고 표면측에서는 소요마스크판(도시치 않음)을 대어 부분 도금을 행한다.Then, the required partial plating is performed as usual on the place where plating is required. In this case, partial plating is performed by placing an upper plate (not shown) on the rear surface side of the lead frame and a required mask plate (not shown) on the surface side.

이 경우에 상기 공정으로 형성된 회로패턴의 리드간의 간극에 도금액이 누출해도 도금액을 회로패턴의 미가공부 단면과 마스크판에 의해서 눌리므로 그 이상 외측으로 누출되는 일은 없다.In this case, even if the plating liquid leaks into the gap between the leads of the circuit pattern formed by the above process, the plating liquid is pressed by the end surface of the unprocessed portion of the circuit pattern and the mask plate.

상기와 같이 부분도금을 행한후에 상기의 나머지 미가공부분의 회로패턴을 프레스가공 또는 에칭가공에 의해서 형성하는 것이다. 제 2 도의 예에서는 댐바 14의 내측부분의 미가공부분(파선부)의 패턴형성을 행한다. 이렇게 함으로써 적어도 댐바 14와 모울드라인 A간의 반도체장치 본체보다도 외측으로 노출되는 외부리드 12의 측단면이 새롭게 형성되므로 측단면에 도금피막이 없는 외부리드 12가 형성된다. 모울드라인 A보다 내측의 회로패턴부는 모울드수지에 의해서 덮이므로 가령 리드측 단면에 은도금피막이 형성되었다 할지라도 마이그레이숀 등의 문제는 극히 생기기 어렵다. 또 부분도금전의 상기 미가공 회로패턴의 범위는 댐바 14보다도 내측으로 모울드라인 A보다도 약간 내측정도에 멍춰놓는 것이 좋다. 즉, 모울드라인 A보다도 약간 내측의 내부리드 10은 그 폭도 넓고, 따라서 미가공부분을 가공할때의 미스매치가 있었다할지라도 그 영향은 작고 리드의 변형등을 초래할 우려가 없기 때문이다. 제 3 도는 상기의 미가공부분을 댐바 14보다 내측에서 모울드라인 A보다도 약간 내측에서 멈추고 부분도금후에 미가공부분을 가공할때에 바로 가까운 내측의 리드사이의 간격보다도 폭넓게 뚫어내어 리드와 댐바 14로의 연결부를 외부리드와 같은 폭이 되도록 가공하고 있다. 그럼으로써 리드프레임을 모울드수지로 덮을때에 리드돌출부 B가 모울드수지에 들어박혀 리드프레임이 빠지지않게하는 앵커로서의 작용을 한다. 이와같이 댐바 14 바로 가까운 내측을 폭넓게 뚫어내어 리드돌출부 B를 앵커로 하는 경우에는 프레스가공의 미스메지는 신경쓰지 않아도 행해지므로 바람직하다.After partial plating as described above, the circuit pattern of the remaining unprocessed portion is formed by press working or etching processing. In the example of FIG. 2, the pattern formation of the unprocessed part (broken part) of the inner part of the dam bar 14 is performed. In this way, at least the side cross-section of the outer lead 12 which is exposed to the outside of the semiconductor device body between the dam bar 14 and the mold line A is newly formed, so that the outer lead 12 having no plating coating is formed on the side cross-section. Since the circuit pattern portion inside the mold line A is covered by the mold resin, even if a silver plated film is formed on the end surface of the lead side, problems such as migration and the like are extremely unlikely to occur. In addition, it is preferable that the range of the raw circuit pattern before partial plating be squeezed to the inside of the dam bar 14 to be slightly inside the mold line A. In other words, the inner lead 10 slightly wider than the mold line A has a wider width. Therefore, even if there is a mismatch when machining the unprocessed portion, the influence is small and there is no fear of causing deformation of the lead. FIG. 3 shows the connection between the lead and the dambar 14 by stopping the above-mentioned raw part from the inside of the dam bar 14 slightly inside the mold line A, and drilling a wider area than the gap between the inner leads immediately near the time of machining the unprocessed part after the partial plating. It is machined to have the same width as the outer lead. Thus, when the lead frame is covered with the mold resin, the lead protrusion B is embedded in the mold resin to act as an anchor to prevent the lead frame from falling out. Thus, in the case where the lead protrusion B is used as an anchor by widely drilling the inner side immediately near the dam bar 14, it is preferable because the mismatch of the press working is performed without concern.

이상과 같이 본 발명에 의하면, 도금액이 가령 리드간에 누출되어 리드측단면에 도금피막이 형성되었다할지라도 도금피막이 형성되는 범위는 장래 반도체장치 본체내에 매설되는 부분이고 반도체장치 본체에서 외측으로 노출되는 외부리드 측단면에는 도금피막이 형성되지 않으므로 마이그레이숀등의 우려가 없는 리드프레임을 제공할 수 있다. 또 댐바와 내부리드 선단과의 사이의 가공에서 보면 2공정으로된 뚫는 가공만으로되고 미가공부분을 도금필요장소로 부터 멀리 떨어뜨림으로서 후공정에서의 미가공부분의 가공이 폭이 넓은 리드부분의 위치에서 행할 수 있으므로 절단선 불일치(미스매치)에 의한 리드의 변형등을 그다지 신경쓰지 않고 행할 수 있는 등의 이점을 갖는다.According to the present invention as described above, even if the plating liquid leaks between the leads and thus the plating film is formed on the lead side end surface, the plating film is formed in the future and is an external lead exposed to the outside from the semiconductor device body. Since no plated film is formed on the side cross section, it is possible to provide a lead frame without fear of migration or the like. In addition, in the process between the dam bar and the inner lead end, only the two-stage drilling process is performed, and the unprocessed part is separated from the place where plating is required, so that the process of the unprocessed part in the post process is performed at the position of the wide lead part. Since it can be performed, it is possible to carry out without paying much attention to deformation of the lead due to cut line mismatch (mismatch).

Claims (1)

외부리드사이를 연결하는 댐바를 갖고 적어도 내부리드의 도금필요장소에 은도금, 금도금등의 부분도금이 행해지는 리드프레임의 가공방법에 있어서, 형성해야할 회로패턴중 반도체장치에 조립했을때 반도체장치 본체내에서 또 상기 도금필요장소에 도달되지 않는 위치와 상기 댐바와의 사이의 회로패턴을 제외하고 적어도 상기 도금필요장소가 되는 부분의 회로패턴의 적어도 측단면을 형성하는 가공을 행하고 그런후에 상기 도금 필요장소에 소요부분 도금을 행하고 다음에 남은 미가공부분의 회로패턴을 형성시키는 가공을 행하는 것을 특징으로 하는 리드프레임의 가공방법.In a method of processing a lead frame having a dam bar connecting between outer leads and partially plating silver plating, gold plating, etc. at a place where plating of the inner lead is necessary, when the semiconductor pattern is formed in a semiconductor device, And at least the side cross-section of the circuit pattern of the part which is to be plated at least except for the circuit pattern between the position where the plated place is not reached and the dam bar, and then the plating place is required. A process for processing a lead frame, characterized in that for performing plating to form a required portion and then forming a circuit pattern of the remaining unprocessed portion.
KR1019890017849A 1988-12-06 1989-12-04 Manufacture of lead frame KR930002816B1 (en)

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JP63308361A JP2648353B2 (en) 1988-12-06 1988-12-06 Lead frame manufacturing method
JP63-308361 1988-12-06

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KR930002816B1 true KR930002816B1 (en) 1993-04-10

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KR100641512B1 (en) 2002-12-30 2006-10-31 동부일렉트로닉스 주식회사 Gold printed lead frame
KR100789419B1 (en) * 2006-11-27 2007-12-28 (주)원일사 Basic material processing method for lead frame
JP6518547B2 (en) 2015-08-07 2019-05-22 新光電気工業株式会社 Lead frame, semiconductor device and method of manufacturing lead frame

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