KR920015972A - 고속, 고밀도용의 칩 배치에 대한 전자부품 조립방법 - Google Patents

고속, 고밀도용의 칩 배치에 대한 전자부품 조립방법 Download PDF

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KR920015972A
KR920015972A KR1019920000911A KR920000911A KR920015972A KR 920015972 A KR920015972 A KR 920015972A KR 1019920000911 A KR1019920000911 A KR 1019920000911A KR 920000911 A KR920000911 A KR 920000911A KR 920015972 A KR920015972 A KR 920015972A
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substrate
chip
edge
pad
electronic component
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KR1019920000911A
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엘. 휠러 리차드
케이. 나제쉬 보다라할리
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하버트 알. 슐츠
휴렛트 팩카드 캄파니
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Publication of KR920015972A publication Critical patent/KR920015972A/ko

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Abstract

내용 없음

Description

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (18)

  1. 기판에 에지 실장하기 위한 전자부품이, 활성 주요면 및 상기 활성 주요면과 수직인 기판부착 에지를 가지며, 상기 활성 주요면은 상기 기판 부착 에지보다 큰 면적을 가지는 집적회로 칩과, 상기 기판부착 에지에 인접하게 상기 활성 주요면의 주연부를 따라 놓여진 복수개의 신호 패드를 포함하므로써 상기 패드는 상기 기판부착에지와 평행하게 배치된 상기 기판의 접점 패턴과 전기적 접속을 제공하는 전자부품.
  2. 제1항에 있어서, 상기 신호 패드가 납을 상기 기판상의 상기 접점 패턴에 직접 접속하기 위해 그 위이 납범프를 갖는 전자부품.
  3. 제1항에 있어서,상기 집적회로 칩이 메모리 칩인 전자부품.
  4. 제1항에 있어서, 상기 집적회로 칩이 상기 기판부착 에지상에서 비활성 층을 갖는 다이인 전자부품.
  5. 제4항에 있어서, 상기 비활성 층이 상기 다이의 각 에지상에 있는 전자부품.
  6. 제1항에 있어서, 상기 칩과이ㅡ 신호 통신은 상기 활성 주요면상의 상기 신호 패드로 국한되는 전자부품.
  7. 평평한 표면사이에 복수개의 접점 패턴을 갖는 기판과, 상기 평평한 기판표면에 실장된 복수개의 전자부품을 포함하며, 각각의 상기 부품은 대향된 주요면들 및 대향된 작은 에지들을 가지며, 상기 대향된 주요면들 간의 치수는 실질적으로 상기 대향된 작은 에지들 간의 치수보다 상당히 작으며, 상기 각 부품의 상기 주요면들 중의하나는 활성표면으로서 상기 작은 에지들중의 제1에지에 인접한 신호패드 패턴을 가지며, 상기 각 부품의 상기 작은 제1에지는 상기 평평한 기판표면에 평행하게 고정되며, 상기 신호 패드의 패턴은 상기 평평한 기판표면상의 상기 접점 팬턴중의 하나에 직접 부착되는 전자부품의 조립체.
  8. 제8항에 있어서, 상기 신호 패드의 패턴은 납범프에 의해 상기 평평한 기판표면상의 상기 접점 패턴에 접속되며, 상기 전자부품은 집적회로 칩인 조립체.
  9. 제8항에 있어서, 상기 기판과 칩간의 신호 통신은 상기 납범프를 통해 처리되는 조립체.
  10. 제7항에 있어서, 상기 부품으로부터 열에너지를 전도시키기 위한 냉각수단을 더 포함하는 조립체.
  11. 제10항에 있어서, 상기 냉각수단은 상기 복수개의 전자부품을 따라 냉각 유체를 흐르게 해주는 유체공급원인 조립체.
  12. 제10항에 잇어서, 상기 수단이 히트 싱크인 조립체.
  13. 제7항에 있어서, 상기 전자부품은 집적회로 칩이며,각 칩은 그것의 에지상에 비활성 층을 갖는 조립체.
  14. 복수개의 전자부품을 상호 접속하는 방법이, 대향된 큰 면적의 주요면 및 상기 주요면의 대응하는 말단부들을 이격시키는 하나의 작은 면적의 장착면을 각기 포함하고, 상기 대응하는 말단부들 간의 거리는 상기 말단부에수직인 상기 주요면의 치수보다 작은 복수개의 집적회로를 칩을 제조하는 단계와, 상기 복수개의 칩상에서, 상기주요면의 제1면상에서 상기 제1주요면의 말단부와 인접하게 복수개의 신호패트를 형성하는 단계와, 복수개의기판패드 패턴을 갖는 기판을 제공하는 단계와, 상기 신호패턴들 상기 기판 패드에 접속시키으로서 상기 각 칩의상기 실장면을 상기 기판에 평행하게 부착하는 단계를 포함함으로서, 고밀도칩 용에 적합한 조립체를 제공하는방법.
  15. 제14항에 있어서, 상기 칩 제조 단계는 반도체 웨이퍼에서 다이를 잘라내고 상기 다이의 에지를 상기 기판에의 부착단계를 위한 비활성 층으로 도포하는 것을 포함하는 방법.
  16. 제14항에 있어서, 상기 칩 제조 단계는 상기 신호 패드위에 납범프를 형성하는 것을 포함하는 방법.
  17. 제16항에 있어서, 상기 칩을 상기 기판에 부착하는 단계는 상기 납펌프를 상기 기판 패드에 납땜하는 것을 포함하는 방법.
  18. 제 14항에 있어서, 상기 기판에 장착된 칩들을 가로질러 냉각 유체가 흐르게해주는 단계를 더 포함하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920000911A 1991-01-24 1992-01-23 고속, 고밀도용의 칩 배치에 대한 전자부품 조립방법 KR920015972A (ko)

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US07/645,913 US5113314A (en) 1991-01-24 1991-01-24 High-speed, high-density chip mounting
US645,913 1991-01-24

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JPH07170098A (ja) 1995-07-04

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