KR920005922B1 - Dial pulse measuring circuit - Google Patents

Abstract

The dial pulse detecting circuit detects the digit value of a dial pulse and the make and break time of a dial pulse. The circuit includes a line interface unit (30) for generating hook off detection signal and clock signal, a dial pulse counter (110) for counting the inverted hook off detection signal, a control signal generator (120) for generating a first control signal by dividing the hook off signal into halves, and a second control signal becoming the first state when make of the first dial pulse ends, a make time detector (130) for counting the clock signal when the first control signal and the hook off detection signal are the first state, a break time detector (140) for counting the clock signal when the first control signal and the inverted hook off signal are the first state, and a digital I/O interface unit (60) for sending dial pulse count value and the detected make/ break time to a digital I/O unit (20).

Description

Dial pulse measuring circuit

1 is a system block diagram of the present invention.

FIG. 2 is a detailed circuit diagram of the count and measurement unit in FIG.

3 is an operation state table and waveform diagram of a dial pulse count unit in FIG. 2;

4 is an operation waveform diagram of a make / brake time measuring unit in FIG. 2.

* Explanation of symbols for main parts of the drawings

41,45,47: Inverter 42,50,51,55,57: Counter

44,46: flip-flop 43,52,56: latch

48,53: NAND gate 49,54: OA gate

The present invention relates to a circuit for measuring a dial pulse transmission function in performing the trunk line interface function of a private exchange and the facsimile line interface function of a telephone. In particular, the digit value of the dial pulse and the make / break of the dial pulse (make The present invention relates to a dial pulse measuring circuit capable of measuring time.

In general, in order to measure dial pulse transmission function among the trunk line interface function of a private exchange and the line interface function of a telephone and a facsimile, an expensive measuring device called 'sysgeration' is conventionally used. The measuring equipment was operated by the tester by manually operating the key, and the determination of the measurement result was performed by the tester directly by looking at the dial pulse value and the make / break rate displayed on the front of the measuring instrument to determine whether the product was defective or defective. Had been done.

However, in the above case, despite the use of expensive measuring equipment, there is a problem that a separate test manpower is required because there is no self-determination ability.

In addition, when using in conjunction with a PC (Personal Computer) to have an automatic measurement function to solve the above problems, it is difficult to purchase a separate option board (for GP-IB) and develop appropriate software. It was.

Accordingly, an object of the present invention is to provide a dial pulse measuring circuit which can automatically measure a dial pulse transmitting function simply by using a digital input / output device of a PC without an expensive measuring instrument or a separate option board.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an embodiment of a system to which the present invention is applied, which has a digital input / output unit 20, a PC 100 for actually controlling and testing a test target equipment, and equipment for transmitting dial pulses ( 300 and a test equipment interface circuit 200 which measures whether the dial pulse transmission function of the equipment 300 is good under the predetermined control through the digital input / output unit 20 of the PC 100.

The test equipment interface circuit 200 inputs a dial pulse from the equipment 300 to generate a hook-off detection signal (HOS) and a clock signal (CLK), and a line interface unit (30). A count and measurement unit 40 for counting and measuring the make / break time of the dial pulse, and data communication between the digital input / output unit 20 of the PC 100 and the count and measurement unit 40. Digital input / output interface unit 50 for controlling.

FIG. 2 is a detailed circuit diagram of the counting and measuring unit 40 in the test equipment interface circuit 200 of FIG. 1, and includes a dial pulse count unit 110, a control signal generator 120, a make detector 130, And, the brake detection unit 140 is made and the specific configuration of each part is as follows.

The dial pulse counting unit 110 may include a first inverter 4l for inverting the hookoff detection signal HOS, a first counter 42 for counting the output of the first inverter 41, and the first inverter 42. The output of the counter 42 consists of the first latch 43.

The control signal generator l20 inverts the first flip-flop 44 which bisects the output of the first inverter 41 to generate the first control signal S1, and the first signal S1. And a second flip-flop 46 which generates a second signal S2 in a first state in synchronization with the output of the second inverter 45.

The make time measuring unit 130 may include a first NAND gate 48 that logically combines the first control signal S1 and the hook-off detection signal HOS, and an output of the first NAND gate 48. The first or gate 49 for ORing the clock signal CLK, the second counter 50 for counting the output of the first or gate 49, and the carry output of the second counter 50 are counted. A third latch 51 and a second latch 52 are configured to output the second and third counters 50 and 51 in synchronization with the second control signal S2.

The break time measuring unit 140 may include a second NAND gate 53 for logically combining the output of the first inverter 41 and the first control signal S1, and the output of the second NAND gate 53. The second or gate 54 for ORing the clock signal CLK, the fourth counter 55 for counting the output of the second oracle 54, and the carry output of the fourth counter 55 are counted. And a third latch 56 by latching the outputs of the fourth and fifth counters 55 and 57 in synchronization with the fifth counter 57 and the second control signal S2.

The present invention will be described in detail based on the above configuration.

Prior to describing the operation, the control signals applied for the performance of the present invention will be described first, and the hook-off detection signal HOS and the clock signal CLK generated by the line interface unit 30 of FIG. It is input to the count and measurement unit 40 showing the concrete circuit in FIG. 2, wherein the hook-off detection signal (HOS) is a high state when making a dial pulse and a low state when a break pulse is transmitted. Is generated and input, and a frequency signal of 4KHZ is input to the clock signal CLK using crystal oscillation.

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,E6)를 발생하여 본 발명 회로의 각 부분을 제어하게 된다.In addition, as a result of decoding or buffering a control bit signal through the control bus 25 from the digital input / output unit 20 built in the PC 100 in the digital input / output interface unit 60 of FIG. Sixth enable signal (

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And E6) to control each part of the circuit of the present invention.

Referring to the operation process of the present invention as follows.

First, the dial pulse counting operation by the dial pulse count unit 110 will be described.

When the dial pulse is transmitted from the device 300 generating the dial pulse, such as an exchange, a telephone, a facsimile, a hook-off detection signal (HOS) is input from the line interface unit 30. At this time, the hook-off detection signal HOS passes through the first inverter 41 and is inverted as illustrated in FIG. 3A.

The inverted hook-off detection signal HOS is input to the first counter 42. The first counter 42 has several inverted hook-off sensing signal Hos pulses as shown in 3b. Count whether it is input.

)를 하이상태로 발생하여 상기 카운트한 값이 제1래처(43)에 래치되게 하고 제1인에이블신호(

)를 로우상태로 하여 상기 제1래치(43)에 래치된 값을 상기 PC(100)에서 읽어서 다이얼펄스가 몇개 입력되었는지 감지하게 함으로써 장비(300)의 다이얼펄스 송출이 양호한지 여부를 판단할 수 있게 한다.When the first counter unit 42 outputs the counted value, the PC 100 transmits the second enable signal through the digital input / output unit 20.

) Is generated in a high state so that the counted value is latched in the first latcher 43 and the first enable signal (

) To determine whether the dial pulse transmission of the device 300 is good by reading the value latched in the first latch 43 from the PC 100 and detecting how many dial pulses are input. To be.

Next, the make time measurement will be described. When the dial pulse is transmitted from the apparatus 300, the line interface unit 30 generates a hook-off detection signal (HOS), as shown in (4a) of FIG. When the pulse is a make, the hook-off detection signal (HOS) is kept high, and when the brake is off, the hook-off detection signal (H0S) is kept low.

)에 의해 리세트되어 있으므로 반전출력단자(

)가 하이상태를 유지한다.The generated hook-off detection signal (HOS) is inverted as shown in (4b) via the first inverter 41 and then input to the second NAND gate 53 and simultaneously supplied to the clock terminal of the first flip-flop 44. The first flip-flop 44 is normally a third enable signal (in a low state)

Inverted output terminal ()

) Stays high.

)로 부터 출력된 신호가 입력단자(D)로 다시 입력되므로 이분주되어 상기 반전된 후크오프 감지신호(HOS)가 클럭단자로 공급되면 비반전출력(Q1)은 (4C)와 같이 하이상태로 되어 제2인버터(45)와 제1및 제2낸드게이트(48,53)로 입력된다.However, the inverting output terminal (

Since the signal output from) is input back to the input terminal (D), when the inverted hook-off detection signal (HOS) is supplied to the clock terminal, the non-inverting output (Q1) is brought to a high state as shown in (4C). And input to the second inverter 45 and the first and second NAND gates 48 and 53.

The signal input to the second inverter 45 is inverted and input to the second flip-flop 46 and the second flip-flop 46 of the second flip-flop 46 is at the moment when the hook-off detection signal (HOS) pulse becomes the second low state. The output goes high like (4g).

In this case, the first NAND gate 48 logically combines the hook-off detection signal HOS and the first control signal S1 output from the first flip-flop 44 to form two input signals as shown in (4d). At the same time, the output of the low state is generated only during the high state, and when the input signal is in a different state, the high state output is generated and input to the first or gate 49.

The first or gate 49 transmits a clock signal CLK (4KHZ) to the second counter 50 only when the output of the first NAND gate 48 is low as shown in 4e. Control 50 so that the clock signal CLK can be counted.

However, when the output of the first NAND gate 48 is in a high state, the output of the first oA gate 49 is always in a high state regardless of the input state of the clock signal CLK. The count operation is not performed because it is not input to the clock terminal of the second counter 50.

The second and third counters 50 and 51 receive a clock signal CLK at the input clock stage and count the number of clocks to output to the second latch 52.

At this time, it can be seen that the clock signal input to the second counter 50 is input during the first pulse make and the third pulse make of the hookoff detection signal 4a as in (4e).

In addition, since the first and third counters 50 and 51 perform a counting operation while a clock signal is input, the first and third counters 50 and 51 are counted several times according to a dial pulse, but are output from the second flip-flop 46. The signal S2 is converted into a high state as shown in FIG. 4G only at the end of the make of the first pulse of the hookoff detection signal HOS, and thus is operated in synchronization with the second control signal S2. The latch 52 latches only the first counted value among the counted values of the clock CLK.

Therefore, the make time can be measured by reading the latched data and calculating the number of clocks generated during make of the dial pulse.

Next, the break time measurement will be described. The output signal of the first inverter 41 and the first control signal S1 output from the first flip-flop 44 are input to the second NAND gate 53. ) Is inputted in the low state only when the output signal of the first inverter 41 and the first control signal S1 are at the same time as the output waveform 4i, and when the two input signals are different from each other. It goes high.

Therefore, the output signal state of the second OA gate 54 which logically combines the second NAND gate 53 output signal and the clock signal CLK is related to the other input clock when the NAND gate 53 output is high. Since the clock signal of the fourth counter 55 is not input to the clock terminal of the fourth counter 55, the clock signal remains the same as the output waveform 4j when the output of the second NAND gate 53 is low. It is input to the fourth counter 55. At this time, the fourth counter 55 counts the number of input clocks and outputs the counted value to the third latch 56. At this time, the clock is counted while the clocks are input to the fourth and fifth counters 55 and 57, like the output waveform 4k. When the clock is input to the counter as shown in the output waveform 4i (time when the output of the second NAND gate 53 becomes low), the hook-off detection signal HOS is the first low state and the third low state. When

The fourth and fifth counters 55 and 57 count twice while the hook-off detection signal HOS goes to the first low state and the third low state while the dial pulse is transmitted. The counted output is latched to the third latch 56 only at the moment when the second control signal S2, which is the output of the second flip-flop 46, becomes high, so that the hook-off is shown in (41). Only the counted value is latched while the sense signal HOS is in the first low state.

)를 로우상태로 되게 제어함으로써 상기 제3래치(56)에 래치된 주파수 카운트 값을 읽어서 브레이크 시간을 계산하여 장비(300)의 다이얼펄스 송출시 브레이크 시간이 양호한가를 측정한다.Meanwhile, in the PC 100, the fifth enable signal (eg, through the digital input / output unit 20)

) Is set to the low state, and the brake time is calculated by reading the frequency count value latched to the third latch 56 to determine whether the brake time is good when the device 300 transmits the dial pulse.

The make / break ratio is obtained by dividing the data value counted at make by the value counted at break.

As described above, it is possible to automatically perform dial pulse transmission test by constructing a product function measurement test equipment at low cost without developing expensive instruments or GP-IB option boards and complicated software. There is an economical advantage in building measurement equipment.

Claims (1)

Having a digital input / output unit 20 and a first to sixth enable signals (

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In a circuit having a PC 100 generating E6 and a device 300 for transmitting dial pulses, a dial pulse is input from the device 300 to provide a hook-off detection signal (HOS) and a clock signal. The line interface unit 30 generating the CLK, the dial pulse count unit 110 for counting and latching the inverted hook-off detection signal, and the inverted hook-off detection signal are divided into two parts, and the first control signal ( And generating a second control signal S2 which is synchronized with the inverted signal of the first control signal S1 and becomes a first state at the end of the make of the first pulse of the hook-off detection signal HO. When the generated control signal generator 120, the first control signal S1, and the hook-off detection signal HOS are both in the first state, the clock signal CLK is counted, but the second control signal ( A make time measurement unit 130 for latching the value only at the moment when S2) is in the first state, and the first agent A break time measuring unit for counting the clock signal when the signal S1 and the inverted hook-off detection signal are both in the first state, but latching the value only when the second control signal S2 is in the first state ( 140 and the first and sixth enable signals to the count and measurement unit 40.

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The digital input / output interface unit 60 transmits E6) and transmits the dial pulse count value and the make / break time measurement value detected from the count and measurement unit 40 to the digital input / output unit 20. Dial pulse measuring circuit, characterized in that.

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