SU1208609A2 - Analyzer of code sequences of pulses - Google Patents

Abstract

The invention relates to a measuring technique and a communication technique, can be used to verify the operability of digital circuits, cable, fiber-optic communication lines and is an improvement of the invention according to the author. St. No. 1023655. The purpose of the invention is to enhance the functionality by providing measurement of the error rate at any sampling rate. The device contains an input unit 1, an allocator 2. errors, 3 errors counter, control block 4, calculator 5, synchronizer 6, timer 7, scoreboard 8 degrees, indication board 9, element 10 OR, two elements 11, 12 AND-NO, RS-flip-flop 13, two D -trigger 14, 15, two multiplexers 16, 17, quartz oscillator 18 and four decade counters 19, 20, 21, 22. 1 Il. (L 1C o CX) Cd O; o

Description

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The invention relates to measurement and communication technology, may be used to verify the operability of digital microcircuits, cable and fiber-optic communication lines and is an enhancement of the invention according to the author. St. No. 1023655.

The purpose of the invention is to expand the functional capabilities of the analyzer by providing an error rate measurement at any sampling rate.

The drawing shows the functional diagram of the device.

The pulse code sequence analyzer contains an input unit 1 connected in series, a 2 error slot and a 3 error counter, the clock input of the 2 error divider connected to the bus Clock, control unit 4 consisting of memory unit 4.1 and keyboard 4.2, calculator 5, synchronizer 6, timer 7, scoreboard 8 degrees, scoreboard 9 indications, element 10 OR, first; and second and second elements 11, 12 AND- NOT, K5 trigger 13, first and second) triggers 14, 15, first multiplexer 16, the second multiplexer 17, performed on buffer cascades 17.1-17.4, quartz oscillator 18, the first decade counter 19, consisting of h bits 19.1-19.Vi, the second decade counter 20, consisting of three bits 20.1-20.3, as well as the third and fourth decade counters 21, 22.

The device works as follows: g; way.40

The code sequence of pulses from the output of the object under study is fed to the input unit 1, which normalizes the incoming signals in amplitude and form. The 2 error selector detects a violation of the structure of the original sequence and generates error signals at the input

counter 3 errors.

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Using the control unit 4, the operation mode of the timer 7, the 3 error counter and the calculator 5 is set. To achieve a certain measurement accuracy, the control unit 4 provides 55 either the error counter 3 or the electronic timer 7 to fix a certain number of errors 30

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RC, or determine the error rate during the exposure time.

Before the next measurement, the signal from the control unit 4 resets the 3 error counter to the zero state, preparing it for the next measurement. The same signal goes to element 10 OR, which serves to amplify this signal. The signal coming from the output of element 10 OR has zeroed the VI — a decade day counter 19, a three-digit day decade counter 20, counters 21 and 22, RS-flip-flop 13 and D-flip-flops 14, 15. At the inputs of elements 11, 12 NO signals are received that allow the passage of the Tact signals. to the input of the decade decade counter 19 and the signals from the output of the crystal oscillator 18 to the input of the three decade decade counter 20. The decadal counter 21 is preset to the zero state. The signals from its outputs go to the control inputs of the multiplexer 16, allowing the transfer of the first-digit transfer signal to its output h-decade counter 19. When the output of the discharge is. A 19.1 decade counter 19 appears a transfer pulse, it is simultaneously recorded in a decade counter 21, i.e. unit is added to the content of the latter. This information is fed to the inputs of the multiplexer 16, allowing the transfer signal to pass to its output from the second bit 19.2 of the decade counter 19.

The pulses from the output of the crystal oscillator 18 are fed to the input of a three-bit decade counter 20. When a transfer pulse appears at the output of the second bit 20.2 of this counter, the state of the D-flip-flop 15 changes. After that, the output signal of the multiplexer 16 arrives at the synchronous input of D-flip-flop 14, changes its state. The signal from its inverse output throws the RS-flip-flop 13, which causes the prohibition signals to the inputs of the elements 11, 12 AND-NOT. As a result, the number dBc is recorded in a three-bit decade counter 20, where Q is any number from 1 to 9, b is any number from O to 9. Thus, the number of clock pulses of a quartz generator is recorded in a three-bit counter 20

Tact signal, i.e. the numerical value of the clock period T.

If the clock frequency f of the crystal oscillator 18 is equal to 10 Guy, then

T „ha-bc.) Where o (- counter readings 21.

Thus, to determine, one can a priori not know the values of the clock frequency and determine the error rate when transmitting any code signal. After the measurement process has been completed, signals from the synchronizer 6 are read in the period or clock frequency values from the control unit 4 or through the multiplexer 17 from the three-discharge counter 20 and counter 22,

The number of errors and the numerical value of the error rate, obtained as a result of arithmetic operations, are displayed on the scoreboard 9 numbers, and the values of the exponent - on the scoreboard 8 8 exponents.

Claims (1)

Invention Formula Pulse code sequence analyzer auth.St. No. 1023655, characterized in that, in order to extend the functionality by providing measurement of the error rate at any sampling frequency, the OR element, the first and second AND-NOT elements, the RS flip-flop, the first and second D-flip-flops, the first and second multiplexers, crystal oscillator, first, second, third five 0 five 0 five And the fourth decade counters, the output of the control unit through the OR element is connected to the set-ups of the RS-flip-flop, the first and second) triggers and all ten-day counters, the output of the first AND-NOT element is connected to the information input of the first ten-day counter, the output outputs of which are connected to corresponding inputs of the first multiplexer,) whose control input is combined with the first input of the second multiplexer and connected to the output of the third decade counter, and the output connected to the inputs of the third decade counter and about 1 -triggera, inversnsh. the output of which is connected to the S-input of the RS flip-flop, the inverse output of which is connected to the first input and the first and second elements AND-NOT, the second input of the second element AND-NOT connected to the output of the quartz oscillator, and the output to the information input of the second decade counter The bit outputs of which are connected to the corresponding inputs of the second multiplexer, the control inputs of which are connected to the corresponding outputs of the fourth decade counter, the synchronization input of which is connected to the synchronizer output, and the output is combined with and moves the second multiplexer connected to a respective input of the control unit, an output of the second discharge of the second decade counter connected to the input of the second D-trigger whose output is connected to the second input of the first D-flip-flop.