US4799023A - Circuits and apparatus which enable elimination of setup time and hold time testing errors - Google Patents
Circuits and apparatus which enable elimination of setup time and hold time testing errors Download PDFInfo
- Publication number
- US4799023A US4799023A US06/753,366 US75336685A US4799023A US 4799023 A US4799023 A US 4799023A US 75336685 A US75336685 A US 75336685A US 4799023 A US4799023 A US 4799023A
- Authority
- US
- United States
- Prior art keywords
- signal
- data signal
- detection
- transition
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Definitions
- FIG. 7 shows a 2-input AND gate, a pair of input signals to test the operation of the AND gate, and the correct output signal at its output port corresponding to the displayed test input signals.
- This AND gate is tested by observing the digital data stream produced at its output port and comparing this observed data stream with that corresponding to a good (i.e. properly functioning) AND gate.
- the data stream In complex circuits, the data stream must be observed at a number of test points and each of these data streams will typically contain many more bits than the 4 bit data stream of the example in FIG. 7. Because of the large amount of test data generated in a test of a typical digital device, many of the test techniques process the data streams to produce output data which is more easily used by the person performing the test. In one scheme known as transition counting, the test device produces for each data stream a number representing the number of times its associated data stream made a low-to-high or high-to-low transition.
- each data stream is divided by a characteristic polynomial to produce a residue (known as a signature) of significantly shorter length than the data stream.
- a signature is chosen to be 16 or 20 bits long so that the residue can be displayed as a 4 or 5 digit display using a hexadecimal character set.
- Signature analysis is implemented by measuring the signature for each test point of a circuit under test and comparing these signatures with those for a circuit which is known to be good. When these two signature sets are not identical, the circuit under test is considered to be bad. The actual element or elements in the circuit which are bad can often be determined by locating those elements which have input signals with correct signature and yet produce output signals with incorrect signature.
- Each of these digital testing techniques relies on the accurate detection of the data stream being observed.
- One source of possible inaccurate detection of data streams is the occurrence of measurements of the data stream near the times of transitions in the data streams. When this occurs, small variations between circuits can cause a data stream for one unit under test to be detected slightly before such transitions while causing the corresponding data stream for another unit under test to be detected slightly after such transitions. This problem in the testing technique could therefore produce a "bad" signature for a unit under test thereby causing some "good units" to be tested as being bad.
- digital data does not make low-to-high or high-to-low transitions along the square wave curves drawn to represent idealized data streams. These transitions instead occur along curves with finite slope so that there is a non-zero time for such transitions.
- rapid transitions are accompanied by transient oscillations which must decay to a certain level before accurate detection of the digital signal can be performed.
- the accurate measurement of digital data requires that a measurement not be initiated within a short time, known as the Setup time T s , after a data transition.
- the measurement process is not instantaneous so that no data transitions should be allowed within a short time, known as the Hold time T h , after a measurement is initiated.
- clock signal In digital devices, data streams throughout the device are typically generated in synchronism with a clock signal. It is therefore natural to utilize such a clock signal to control the selection of times at which the measurement of data streams in a unit under test are performed. In some test situations the clock signal is produced by the unit under test but in other situations the testing device provides the clock signal.
- the clock signal is usually periodic, but in some cases it can be aperiodic.
- the DAV signal can be utilized as the signal controlling the selection of measurement times.
- the signal used to control the times at which measurements are performed on a data signal will be referred to herein as the "detection signal”.
- the particular examples discussed below will be in terms of a periodic detection signal and will be referred to as a clock signal. Because in each of these cases, measurement times are initiated in response to the clock signal, it is important to detect whether the clock signal transitions occur within the interval around the data transitions determined by the Setup time and the Hold time.
- the timing of data transitions relative to clock transitions can vary depending on which test point in a unit under test is being tested.
- contact is made from the HP 3060 to a circuit board under test by means of bed-of-nails contact scheme.
- each test point in the circuit board is contacted by one of a set of test probes in the HP 3060. Therefore, the data gathered at the various test points are subject to relative delays caused by differences in signal delays within the circuit board under test in reaching the test point at which the signal is tested. This measured data is subject to further relative delays because of the variation in delays among the various circuit paths within the HP 3060.
- the detected data at each of the data points can have differing delays relative to the clock signal, so that data at some test points can be accurately tested even though data at other test points is inaccurately tested. It is therefore important to check the timing of the data transitions in each data stream from each of the test points relative to the clock transitions.
- the incidence of the undesired near coincidence of clock and data transitions is detected by first producing from the data signal a supplementary signal having pulses in synchronism with the transitions in the data signal.
- Each of these pulses has a width T 1 +T 2 (where T 1 is the time after a data transition in which a repeatable measurement can't be initiated and T 2 is the time before a data transition in which a repeatable measurement can't be initiated) equal to the width of the window about each transition in which measurements should not be performed.
- the near coincidence of clock and data transitions is checked by delaying the clock signal by the time T 2 and then checking whether the clock signal executes during any of the pulses a transition on which data measurements are triggered.
- a flag is set to apprise the user of that occurrence.
- the person testing the unit under test can select a fixed delay T d by which the clock signal is delayed to eliminate the near coincidence.
- FIG. 1 shows a circuit suitable for detecting a clock trigger edge within the window about a low-to-high data transition defined by the Setup and Hold times.
- FIG. 2 is a timing diagram for the circuit of FIG. 1.
- FIG. 3 shows a circuit suitable for producing pulses of length T 1 +T 2 in response to negative transitions of a data signal.
- FIG. 4 is a timing diagram for the circuit of FIG. 3.
- FIG. 5 shows a variable delay circuit suitable for delaying a signal by a user selectable amount.
- FIG. 6 is a block diagram of a circuit tester capable of detecting whether a clock trigger edge is within a window about a data transition defined by the Setup and Hold times.
- FIG. 7 shows input signals suitable for testing an AND gate to produce an expected output signal.
- FIG. 8 is a block diagram of a circuit tester capable of detecting whether a data transition is within a window about a clock trigger edge defined by the Setup and Hold times.
- FIG. 9 is a block diagram of a circuit tester in which a data signal can be delayed by a controlled amount to eliminate an unwanted near coincidence of a clock trigger edge and transitions in the data signal.
- the output signal of the AND gate is applied to the D input of an edge sensitive D-type flip-flop 15.
- the clock signal is applied to a clock line 16 which is connected through a delay circuit 17 to the clock input of flip-flop 15.
- the relationship between the delayed clock signal and the output signal of AND gate 12 is shown in FIG. 2. In that figure it is assumed that measurements are made in response to the low-to-high transition of the clock signal so that the edge sensitive flip-flop is selected to respond to the low- to-high transition of the signal at its clock input Ck. In the opposite case in which measurements are initiated in response to a high-to-low transition of the clock signal, flip-flop 15 is also selected to be responsive to the high-to-low transition of the signal at its clock input Ck.
- delay circuit 14 and 17 are selected to produce delays of T 1 +T 2 and T 2 respectively. This choice of delays will make the delayed clock signal occur during the pulse in the output signal of AND gate 12 only if the clock signal occurs within a time T 1 after the data transition or within a time T 2 before the data transition thereby initiating a measurement during the window about a data transition in which repeatable measurements can't be initiated.
- the combination of elements 11, 12, 13 and 14 will produce a pulse only for low-to-high data transitions.
- the combination of elements 11-14 in FIG. 1 should be replaced by the combination of elements 31-34 in FIG. 3.
- the data signal is applied on a data line 31 which is connected through an inverter 33 to one input of an AND gate 32.
- the data signal is also passed through a delay circuit 34 to the other input of AND gate 32.
- FIG. 4 shows the signals which result in this circuit from the application of the data signal to data line 33.
- the circuit shown in FIG. 1 enables the detection of a clock transition near a low-to-high data transition.
- the substitution of the circuit in FIG. 3 for the combination of elements 11-14 in FIG. 1 enables the detection of clock transitions near a high-to-low data transition.
- the output of AND gate 12 and AND gate 32 could be applied to the inputs of a 2 input OR gate to produce a supplementary signal having pulses at both types of data transitions.
- the application of this supplementary signal to the D input of flip-flop 15 would enable the detection of clock transitions near either type of data transition.
- FIG. 5 One choice of a variable delay circuit is shown in FIG. 5 in which a clock signal is passed through 4 parallel paths having inserted delays of O, D 1 , D 2 , and D 3 respectively.
- a pair of control signals A and B select which of the input lines to Multiplexer 51 is connected to output line 52. Initially, the A and B inputs are both zero to select zero delay. If appear coincidence is detected then the delay is changed to D 1 . If the near coincidence persists then D 2 is selected and finally if D 2 is inadequate then D 3 is selected.
- a data line from each of several test points will supply data. Since each line can have different delays relative to the clock signal, near coincidence might occur for some lines but not others. The choice of more than 2 selections for clock delay improves the chance that one of the choices will eliminate near coincidences for all data times. If in a given test the 4 choices of delay provided by the circuit in FIG. 4 are not sufficient to remove near coincidences of all data and clock transitions, then several alternatives can be employed to accurately test all of the test points. In one alternative, the number and/or range of delays can be increased. In a second alternative, variable delays can be inserted in some or all of the data lines. In a third alternative, only data on lines having no near coincidences will be processed when the choice of delay is zero.
- D 1 For a tester which is constructed to handle clock rates up to 10 megaherz (i.e. clock periods greater than 100 nsec), a useful choice for D 1 , D 2 and D 3 is 30, 60 and 90 nsec respectively. Typical values for the T 1 and the time T 2 are 30 nsec and 20 nsec respectively so that this selection of delays should enable near coincidences with the clock signal transitions of transitions on any given data line to be eliminated.
- FIG. 6 a data tester containing a near coincidence detector 64 like the circuit shown in FIG. 1 and a controllable delay circuit 61 like the circuit shown in FIG. 5.
- a clock signal used to control the times at which data is detected is applied on an input 62 to produce a delayed clock signal 63.
- Near coincidence detector produces on line 65 a signal indicating whether any trigger edges in the delayed clock signal occur within a window defined by the Setup and Hold times about transitions in data applied on a data input 66.
- a detector 67 is utilized to detect the data and provide an output signal on output 68.
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/753,366 US4799023A (en) | 1981-11-05 | 1985-07-05 | Circuits and apparatus which enable elimination of setup time and hold time testing errors |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31852981A | 1981-11-05 | 1981-11-05 | |
US06/753,366 US4799023A (en) | 1981-11-05 | 1985-07-05 | Circuits and apparatus which enable elimination of setup time and hold time testing errors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US31852981A Continuation | 1981-11-05 | 1981-11-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
US4799023A true US4799023A (en) | 1989-01-17 |
Family
ID=26981536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/753,366 Expired - Lifetime US4799023A (en) | 1981-11-05 | 1985-07-05 | Circuits and apparatus which enable elimination of setup time and hold time testing errors |
Country Status (1)
Country | Link |
---|---|
US (1) | US4799023A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5036221A (en) * | 1989-03-31 | 1991-07-30 | Texas Instruments Incorporated | Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal |
EP0514050A2 (en) * | 1991-05-01 | 1992-11-19 | STMicroelectronics, Inc. | Control circuit for dual port memory |
US5471159A (en) * | 1992-09-18 | 1995-11-28 | Tektronix, Inc. | Setup or hold violation triggering |
US6167001A (en) * | 1999-01-26 | 2000-12-26 | Xilinx, Inc. | Method and apparatus for measuring setup and hold times for element microelectronic device |
DE10014386A1 (en) * | 2000-03-23 | 2001-09-27 | Infineon Technologies Ag | Integrated circuit e.g. for synchronous DRAM - has comparator for comparing temporal signal transitions of clock signal with those of digital signal |
US20040251944A1 (en) * | 2003-06-10 | 2004-12-16 | James Ma | Prevention of metastability in bistable circuits |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4237423A (en) * | 1978-12-08 | 1980-12-02 | Rca Corporation | Digital phase detector |
-
1985
- 1985-07-05 US US06/753,366 patent/US4799023A/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4237423A (en) * | 1978-12-08 | 1980-12-02 | Rca Corporation | Digital phase detector |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5036221A (en) * | 1989-03-31 | 1991-07-30 | Texas Instruments Incorporated | Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal |
EP0514050A2 (en) * | 1991-05-01 | 1992-11-19 | STMicroelectronics, Inc. | Control circuit for dual port memory |
EP0514050B1 (en) * | 1991-05-01 | 1999-10-20 | STMicroelectronics, Inc. | Control circuit for dual port memory |
US5471159A (en) * | 1992-09-18 | 1995-11-28 | Tektronix, Inc. | Setup or hold violation triggering |
US6167001A (en) * | 1999-01-26 | 2000-12-26 | Xilinx, Inc. | Method and apparatus for measuring setup and hold times for element microelectronic device |
DE10014386A1 (en) * | 2000-03-23 | 2001-09-27 | Infineon Technologies Ag | Integrated circuit e.g. for synchronous DRAM - has comparator for comparing temporal signal transitions of clock signal with those of digital signal |
US6351161B2 (en) | 2000-03-23 | 2002-02-26 | Infineon Technologies Ag | Integrated circuit with actuation circuit for actuating a driver circuit |
US20040251944A1 (en) * | 2003-06-10 | 2004-12-16 | James Ma | Prevention of metastability in bistable circuits |
US6906555B2 (en) | 2003-06-10 | 2005-06-14 | James Ma | Prevention of metastability in bistable circuits |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4139147A (en) | Asynchronous digital circuit testing and diagnosing system | |
US4428076A (en) | Method of and system for evaluating bit errors in testing a signal path | |
US5122694A (en) | Method and electrical circuit for eliminating time jitter caused by metastable conditions in asynchronous logic circuits | |
US4495621A (en) | Glitch detecting and measuring apparatus | |
US4577318A (en) | Self testing detection system for comparing digital signal transition times | |
GB2100011A (en) | Multi-speed logic analyzer | |
US4603292A (en) | Frequency and time measurement circuit | |
JP2003057314A (en) | Device and method for testing digital device using transition time stamp | |
JPH07181204A (en) | Logic-signal display method | |
US4534030A (en) | Self-clocked signature analyzer | |
JPH0646212B2 (en) | Adjustable system for skew comparison of digital signals. | |
US4646297A (en) | Skew detector | |
US4799023A (en) | Circuits and apparatus which enable elimination of setup time and hold time testing errors | |
JPH04233478A (en) | Method and apparatus for measuring waveform | |
US4385383A (en) | Error rate detector | |
US7495429B2 (en) | Apparatus and method for test, characterization, and calibration of microprocessor-based and digital signal processor-based integrated circuit digital delay lines | |
US4833397A (en) | Tester for verification of pulse widths in a digital system | |
US4578666A (en) | Method of comparing data with asynchronous timebases | |
US3473115A (en) | Method and apparatus for testing magnetostrictive delay lines by checking for signal coincidence between signal pulses and reference pulses in different phase positions of the reference pulses | |
US3057957A (en) | Apparatus for measuring data signal impairment | |
JPS5883433A (en) | Logical level detector | |
KR920005922B1 (en) | Dial pulse measuring circuit | |
SU1132685A1 (en) | Device for measuring pulse voltage-current characteristics of semiconductor materials | |
KR910009668B1 (en) | Apparatus for measuring bit error rate in digital communication system | |
JPS62131637A (en) | Timing jitter measuring system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HEWLETT-PACKARD COMPANY, PALO ALTO, CALIFORNIA A C Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ILLICK, ROBERT C., JR.;FIROOZ, KAMRAN;HARWOOD, VANCE R.;AND OTHERS;REEL/FRAME:004887/0771 Effective date: 19811104 Owner name: HEWLETT-PACKARD COMPANY, A CA CORP.,CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ILLICK, ROBERT C., JR.;FIROOZ, KAMRAN;HARWOOD, VANCE R.;AND OTHERS;REEL/FRAME:004887/0771 Effective date: 19811104 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: HEWLETT-PACKARD COMPANY, A DELAWARE CORPORATION, C Free format text: MERGER;ASSIGNOR:HEWLETT-PACKARD COMPANY, A CALIFORNIA CORPORATION;REEL/FRAME:010841/0649 Effective date: 19980520 |
|
AS | Assignment |
Owner name: AGILENT TECHNOLOGIES INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY, A DELAWARE CORPORATION;REEL/FRAME:010901/0336 Effective date: 20000520 |
|
FPAY | Fee payment |
Year of fee payment: 12 |