KR920005052Y1 - Scanning line position control circuit - Google Patents

Scanning line position control circuit Download PDF

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Publication number
KR920005052Y1
KR920005052Y1 KR2019900002365U KR900002365U KR920005052Y1 KR 920005052 Y1 KR920005052 Y1 KR 920005052Y1 KR 2019900002365 U KR2019900002365 U KR 2019900002365U KR 900002365 U KR900002365 U KR 900002365U KR 920005052 Y1 KR920005052 Y1 KR 920005052Y1
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South Korea
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output
signal
flop
schmitt trigger
gate
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KR2019900002365U
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Korean (ko)
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KR910016032U (en
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김종철
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주식회사 금성사
한태희
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Details Of Television Scanning (AREA)

Abstract

내용 없음.No content.

Description

스캔닝 라인 포지션 콘트롤회로Scanning line position control circuit

제 1 도는 본 고안에 따른 스캔닝 라인 포지션 콘트롤회로도.1 is a scanning line position control circuit diagram according to the present invention.

제 2 도는 본 고안에 따른 각부파형도.2 is an angular waveform diagram according to the present invention.

제 3 도는 본 고안에 따른 슈미트 트리거 앤드게이트 동작설명도.3 is a schematic diagram of Schmitt trigger and gate operation according to the present invention.

제 4 도는 본 고안에 따른 화면상의 스캔닝 라인의 변화표시도.4 is a change display of the scanning line on the screen according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

B1 : 수직동기신호 발생회로 B2 : 스캔닝 라인 포지션 콘트롤회로B1: vertical synchronous signal generating circuit B2: scanning line position control circuit

1 : 수직동기분리기 2, 3 : 플레러티1: vertical synchronous separator 2, 3: purity

D1∼D4 : 다이오드 IC2, IC3 : 슈미트 트리거 앤드게이트D1 to D4: Diode IC2, IC3: Schmitt trigger and gate

IC1 : D플립플롭 IC4 : 모노스테이블ICIC1: D flip-flop IC4: Monostable IC

VR1 : 가변저항 R1∼R3 : 저항VR1: Variable resistors R1 to R3: Resistance

C1, C2 : 가변저항C1, C2: Variable resistor

본 고안은 스캔닝 라인 포지션을 콘트롤하는 회로에 관한것으로 특히 인터레이스(Interace)모드의 모니터에서 그 간격을 정확히 조정하여 화면의 질을 높이도록한 스캔닝 라인 포지션 콘트롤회로에 관한 것이다.The present invention relates to a circuit for controlling the scanning line position, and more particularly, to a scanning line position control circuit for precisely adjusting the interval in an interlace mode monitor to improve the screen quality.

본 고안은 제 1 도에 도시된 것처럼 동기분리기(1)와 폴레러티회로(2,3)로 구성되어 수직동기신호(VA)를 만드는 기존의 수직동기신호 발생회로(B1)와, 상기 수직동기신호 발생회로(B1)에서의 수직동기신호(VA)와 VC(오드/이븐)신호를 입력받아 스캔닝 라인의 포지션을 콘트롤하는 스캐닝 라인 포지션 콘트롤회로(B2)로 구성된다.The present invention comprises a conventional vertical synchronous signal generating circuit (B1) composed of a synchronous separator (1) and a polarity circuit (2, 3) to make a vertical synchronous signal (V A ), as shown in FIG. And a scanning line position control circuit B2 that receives the vertical synchronizing signal V A and the V C (odd / even) signal from the vertical synchronizing signal generating circuit B1 and controls the position of the scanning line.

본 고안 회로의 구성을 좀더 상세히 설명하면, 수직동기신호 발생회로(B1)의 출력(VA)은 스캔닝 라인 포지션 콘트롤회로(B2)내의 슈미트 트리거 앤드게이트(IC2)의 일측입력과 가변저항(VR1) 및 슈미트 트리거 앤드 게이트(IC3)의 일측입력에 동시연결되고 슈미트 트리거 앤드게이트(IC2)의 다른측 입력에는 오드/이븐신호(VC)가 인가되고 슈미트 트리거 앤드게이트(IC2)의 출력은 D-플립플롭(IC1)의 클락신호가 되며 D-플립플롭(IC1)의 입력(D)에는 D-플립플롭(IC1)의출력이 인가되고 D-플립플롭(IC1)의 Q출력(VD)은 다이오드(D4)를 거쳐 다이오드(D3)의 캐소우드와 저항(R1)의 일측 및 슈미트 트리거 앤드게이트(IC3)의 나머지 일측입력으로 공통 연결되고 저항(R1)의 다른측은 접지되며 다이오드(D3)의 애노우드는 가변저항(VR1)과 연결되는 동시에 콘덴서(C1)를 통해 접지되고, 슈미트트리거 앤드게이트(IC3)의 출력(VB)은 모노스테이블IC(IC4)와 연결되고 모노스테이블IC(IC4)의 Q출력(VE)은 D-플립플롭(IC1)의 클리어단자로 연결되는 구성이다.In more detail, the configuration of the circuit of the present invention is described in detail. The output V A of the vertical synchronization signal generating circuit B1 may include one side input of the Schmitt trigger and gate IC2 and the variable resistor in the scanning line position control circuit B2. VR1) and the Schmitt trigger and gate IC3 are simultaneously connected to the input of the other side of the Schmitt trigger and gate IC2, the odd or even signal (V C ) is applied to the output of the Schmitt trigger and gate (IC2) It becomes the clock signal of the D-flop flop IC1 and the input D of the D-flop flop IC1 The output is applied and the Q output (V D ) of the D-flop flop (IC1) passes through the diode (D4), the cathode of the diode (D3) and one side of the resistor (R1) and the other side of the Schmitt trigger and gate (IC3). Commonly connected to the input, the other side of resistor R1 is grounded, the anode of diode D3 is connected to variable resistor VR1 and grounded via capacitor C1, and the output of Schmitttrigger and gate IC3 ( V B ) is connected to the monostable IC (IC4), and the Q output (V E ) of the monostable IC (IC4) is connected to the clear terminal of the D-flop flop (IC1).

상기 구성회로의 동작상태를 설명하면, 제 2 도의 AA파형과 같은 수직동기신호 발생회로(B1)의 출력이 수직 동기신호(VA)가 스캔닝 라인 포지션 콘트롤회로(B2)로 인가되는데 이때 상기의 수직동기신호(VA)와 오드/이븐(ODD/EVEN)신호(VC)를 입력받는 슈미트 트리거 앤드게이트(IC2)의 출력을 클락신호로 인가받는 D-플립플롭(IC1)의 출력(VD)이 '로우'인 경우에는 가변저항(VR1)과 콘덴서(C1)의 시정수에 의해 정해지는 딜레이시간(T1)이 나타나서 슈미트 트리거(IC3)의 출력단에는 제 2 도의 VB와 같은 파형이 출력된다.Referring to the operation state of the configuration circuit, the output of the vertical synchronous signal generating circuit (B1), such as the A A waveform of Figure 2 is applied to the scanning line position control circuit (B2) the vertical synchronizing signal (V A ) The output of the D-flip flop IC1 receiving the output of the Schmitt trigger and gate IC2 receiving the vertical synchronization signal V A and the ODD / EVEN signal V C as a clock signal. When (V D ) is 'low', the delay time T1 determined by the time constants of the variable resistor VR1 and the capacitor C1 appears and the output terminal of the Schmitt trigger IC3 is equal to V B in FIG. The waveform is output.

여기서 D-플립플롭(IC1)의 출력(VD)이 '로우'인 것은 D-플립플롭(IC1)은 매주기마다 모노스테이블IC(IC4)의 출력(VE)에 의해 클리어 되어 있으므로 D-플립플롭의 클락펄스가 인가되기 위해서는 오드/이븐신호(VC)가 '하이'여야 하는데 오드/이븐신호(VC)가 '로우'인 경우 슈미트 트리거 앤드게이트(IC2)의 출력 '로우'이므로 D-플립플롭(IC1)에 클락펄스가 인가되지 않아 D-플립플롭(IC1)의 출력(VD)이 '로우'로 되므로 가변저항(VR1)과 콘덴서(C1)의 시정수만큼의 딜레이시간(T1)을 갖은 뒤 입력수직동기신호(VA)에 따라 출력이 나타나게 된다. (제 2 도의 VB) 만약 제 2 도의 VC신호에서 오드필드(ODD Field)인 경우 ('하이'인 경우) 동기신호(VA)와 VC신호가 동시에 '하이'로되는 기간이 있어 이기간동안 D-플립플롭(IC1)에 클락펄스가 가해지므로 D-플립플롭(IC1)의 Q출력(VD)은 '하이'가 되어 슈미트 트리거 앤드게이트(IC3)의 일측입력단으로 인가되어 동기신호(VA)가 그대로 슈미트 트리거 앤드게이트(IC3)의 출력(VB)이 되므로 딜레이가 나타나지 않는다.Here, the output V D of the D-flop flop IC1 is 'low' because the D-flip flop IC1 is cleared by the output V E of the monostable IC IC4 every cycle. In order for the clock pulse of the flip-flop to be applied, the odd / even signal (V C ) must be 'high'. When the odd / even signal (V C ) is 'low', the output of the Schmitt trigger and gate (IC2) is 'low'. Since no clock pulse is applied to the D-flop flop IC1, the output V D of the D-flop flop IC1 becomes 'low', so that the delay of the variable resistor VR1 and the capacitor C1 is equal to the time constant. After the time T1, the output appears according to the input vertical synchronization signal V A. (V B of FIG. 2) If the V C signal of FIG. 2 is an odd field (ODD field) ('high'), there is a period in which the synchronization signal V A and the V C signal are simultaneously 'high'. During this period, the clock pulse is applied to the D-flop flop IC1, so the Q output V D of the D-flop flop IC1 becomes 'high' and is applied to one input terminal of the Schmitt trigger and gate IC3 to synchronize. Since the signal V A becomes the output V B of the Schmitt trigger and gate IC3 as it is, no delay appears.

여기서 가변저항(VR1)의 값을 조절하여 제 3 도와 같이 슈미트 트리거 앤드게이트 출력신호의 딜레이시간이 T1→T2→T3로 달라지게 할 수 있다. 슈미트 트리거 앤드게이트 출력신호의 딜레이시간 변화는 슈미트 트리거 앤드게이트(IC3)의 출력 수직동기신호(VB)의 라이징 포인트를 다르게 할 수 있음을 의미하므로 화면상에 제4도와 같이 스캔닝 라인의 변화를 가져올 수 있게 된다.In this case, the delay time of the Schmitt trigger and gate output signal may be changed from T1 to T2 to T3 by adjusting the value of the variable resistor VR1. The change in the delay time of the Schmitt trigger and gate output signal means that the rising point of the output vertical synchronization signal V B of the Schmitt trigger and gate IC3 can be changed, so that the scanning line changes as shown in FIG. 4 on the screen. You will be able to import.

따라서 본 고안은 인터레이스 모드의 모니터에서 그 간격을 정확히 조정하므로서 화면의 질을 높이는 효과가 있다.Therefore, the present invention has the effect of improving the screen quality by accurately adjusting the interval in the monitor of the interlace mode.

Claims (1)

수직동기신호 분리기(1)와 플레러티(2,3)로 구성되는 기존의 수직동기신호 발생회로(B1)로 부터의 수직동기신호(VA)와 오드/이븐신호(VC)를 입력으로 받아 그 출력을 D-플립플롭(IC1)의 클락신호로 인가하는 슈미트 트리거 앤드게이트(IC2)와, 상기 슈미트 트리거 앤드게이트(IC2)로 부터의 클락신호에 따라 '하이', '로우'로 콘트롤되는 Q출력(VD)을 다이오드(D4)를 통해 슈미트 트리거 앤드게이트(IC3)의 일측입력으로 인가하는 D-플립플롭(IC1)과, 상기 D-플립플롭(IC1)의 Q출력(VD)이 '로우'이면 가변저항(VR1)과 콘덴서(C1) 의 시정수 만큼 딜레이 시간을 수지공기 신호를 출력하고 상기 D-플립플롭(IC1) Q출력(VD)이 '하이'이면 상기 수직동기신호 발생회로(B1)로 부터의 수직동기신호(VA)를 그대로 출력하는 슈미트트리거 앤드게이트(IC3)와, 상기 슈미트 트리거 앤드게이트(IC3)의 출력(VB)을 입력받고 그 출력(VE)을 D-플립플롭(IC1)의 클리어신호로 인가하는 모노스테이블 IC(IC4)와, 상기 D-플립플롭(IC1)의 Q출력(VD)이 '로우'일 때 슈미트 트리거 앤드 게이트(IC3)의 출력수직 동기신호(VB)의 딜레이 시간을 콘트롤 할수 있는 가변저항(VR1)을 포함하여 구성된 것을 특징으로 하는 스캔닝 라인 포지션 콘트롤회로.The vertical synchronous signal V A and the odd / even signal V C from the existing vertical synchronous signal generating circuit B1 composed of the vertical synchronous signal separator 1 and the solidity 2, 3 as inputs. Control the 'high' and 'low' according to the Schmitt trigger and gate (IC2) and the clock signal from the Schmitt trigger and gate (IC2) to receive the output as a clock signal of the D-flip flop (IC1) D -flip flop IC1 for applying the Q output V D to the one-side input of the Schmitt trigger and gate IC3 through the diode D4, and the Q output V D of the D-flip flop IC1. Is low, outputs a resin air signal with a delay time corresponding to the time constants of the variable resistor VR1 and the capacitor C1, and if the D-flip-flop IC1 Q output V D is high, and synchronizing signal generating circuit (B1) vertical synchronization signal (V a) as a Schmitt trigger aND gate (IC3) for outputting a from the Schmitt trigger and- Byte output (V B) receives the output (V E) a mono Stables IC (IC4) and the D- flip-flop (IC1) to apply a clear signal of the D- flip-flop (IC1) of (IC3) And a variable resistor (VR1) for controlling the delay time of the output vertical synchronization signal (V B ) of the Schmitt trigger and gate (IC3) when the Q output (V D ) is 'low'. Ning line position control circuit.
KR2019900002365U 1990-02-28 1990-02-28 Scanning line position control circuit KR920005052Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019900002365U KR920005052Y1 (en) 1990-02-28 1990-02-28 Scanning line position control circuit

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Application Number Priority Date Filing Date Title
KR2019900002365U KR920005052Y1 (en) 1990-02-28 1990-02-28 Scanning line position control circuit

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KR910016032U KR910016032U (en) 1991-09-25
KR920005052Y1 true KR920005052Y1 (en) 1992-07-25

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