JP2541191B2 - Horizontal image shift circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a horizontal image shift circuit of a monitor receiver to which horizontal synchronizing signals of two or more frequencies are supplied.

[Outline of Invention]

According to the present invention, in the horizontal image shift circuit to which the horizontal synchronizing signals of two or more frequencies are supplied, the frequency voltage converting circuit for converting the frequency of the input synchronizing signal into a voltage and the time corresponding to the output voltage of the frequency voltage converting circuit. , A delay circuit for delaying the input synchronization signal is provided, and even if the frequency of the input synchronization signal is different, the amount of movement of the image on the screen with respect to the volume for image shift is made constant, and the input synchronization signal of a certain frequency When the position of the image is adjusted to the center with respect to, the image is positioned substantially in the center of the screen even with respect to the input synchronizing signals of different frequencies.

[Conventional technology]

15.7 (kHz), 18 (kHz), 22 (kHz), 32 (kHz), 35 so that it can be used as a computer display
Monitor receivers (so-called multi-scan monitors) capable of inputting signals of various horizontal frequencies such as [kHz] are known. When the input video signal is displayed on a multi-scan monitor, the source (computer) may cause the image to not be centered on the screen. To correct this problem, a horizontal image shift circuit that delays the input horizontal synchronizing signal is provided.

Since the timing of the video signal relative to the horizontal sync signal differs depending on the computer or the frequency of the sync signal,
The variable range of the shift amount, that is, the delay amount is set in consideration of the frequency of the computer or the synchronization signal. Also,
The variable range of the delay amount is a value proportional to the cycle of the horizontal synchronizing signal. For example, if the horizontal frequency is 15 [kHz], 8 [μse
c], it becomes about 4 [μsec] at 32 [kHz]. In the conventional image shift circuit, the variable range of the delay amount is set to the predetermined value required when the frequency is the lowest (15.7 [kHz]).

[Problems to be solved by the invention]

6 and 7 show the image shift operation when the horizontal frequencies are different. FIG. 6 shows, for example, that the horizontal frequency is 15.7.
[KHz] (cycle TH1), and FIG. 7 shows a case where the horizontal frequency is 32 [kHz] (cycle TH2), for example. Therefore, there is a relationship of (TH1≈2TH2). 6A and 7A show the video signals supplied to the monitor receiver, respectively, and FIGS. 6B and 7B show the horizontal synchronizing signals supplied to the monitor receiver, respectively. In the image shift circuit for shifting the displayed image to the center of the screen, the horizontal synchronizing signal Hs shown in FIGS. 6B and 7B is delayed and shown in FIGS. 6C and 7C, respectively. A delayed sync signal is formed.

The adjustment volume provided in the image shift circuit is rotated from the minimum position to the maximum position, and the delay amount is added to the horizontal sync signal.
When Td is given, in the case of 15.7 [kHz], the image is horizontally moved by, for example, 5 [cm], and in the case of 32 [kHz], the image is moved by 10 [cm]. That is, the sensitivity of the volume changes depending on the frequency of the input horizontal synchronizing signal Hs.
With respect to the horizontal frequency signal of 15.7 (kHz), when the image is adjusted to the center of the screen and the horizontal frequency signal of 32 (kHz) is input, the shift amount of the image on the screen is 1
Since it is twice as high as that at 5.7 [kHz], the image is largely displaced from the center position, and it is necessary to repeat the adjustment operation.

Therefore, an object of the present invention is to provide an image shift circuit in the horizontal direction in which the amount of image shift on the screen with respect to the volume for horizontal image shift is constant regardless of the horizontal frequency.

[Means for solving problems]

According to the present invention, in a horizontal image shift circuit to which a horizontal synchronizing signal of two or more frequencies is supplied, a frequency voltage converting circuit for converting the frequency of the input synchronizing signal into a voltage and an output voltage from the frequency voltage converting circuit are determined. A constant current circuit for converting into a current, a means for varying the constant current according to the horizontal shift amount, and a delay circuit for delaying the input synchronization signal for a time period according to the value of the constant current, Is a horizontal image shift circuit.

[Action]

The input synchronizing signal is delayed by a delay circuit such as a mono-multi (monostable multivibrator) 2 to form a delayed synchronizing signal. Further, the input synchronization signal is supplied to the frequency-voltage conversion circuit 7, and the frequency-voltage conversion circuit 7 generates a voltage Vs proportional to the frequency of the input synchronization signal. The delay time of the monomulti 2 is controlled according to the output voltage Vs of the frequency-voltage conversion circuit 7. This delay time is reduced as the horizontal frequency increases. Therefore, even when the horizontal frequency of the input signal is different, the shift amount of the image on the screen is constant.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the input synchronization signal Hs is supplied to the input terminal indicated by 1. This input synchronization signal Hs is supplied to the mono-multi 2 and the frequency voltage conversion circuit 7.

The mono-multi 2 is triggered by the input synchronization signal Hs, and the delay time Td set by the variable resistor (volume) for adjustment is generated in the mono-multi 2. Mono Multi 2
The output signal of triggers the mono multi 3. The mono-multi 3 generates a delayed synchronization signal having a predetermined pulse width. This delayed synchronization signal is supplied to the horizontal AFC circuit 4.
A horizontal oscillator 5 is provided in association with the horizontal AFC circuit, and the output signal of the horizontal oscillator 5 is supplied to the horizontal output circuit 6. The horizontal deflection current generated by the horizontal output circuit 6 is supplied to a horizontal deflection coil (not shown).

The output voltage Vs of the frequency voltage conversion circuit 7 is supplied to the constant current circuit 8, and the constant current formed by the constant current circuit 8 is controlled by the output voltage Vs of the frequency voltage conversion circuit 7. This constant current is supplied to the mono-multi 2 as a delay time control signal. The frequency-voltage conversion circuit 7 is composed of a mono-multi and an integration circuit.

FIG. 2 shows an example of a mono-multi. A pair of transistors, shown as 10 and 11, respectively, is provided, and a capacitor 15 is provided between the base of the transistor 10 and the collector of the transistor 11.
A parallel circuit of a resistor 16 and a resistor 16 is inserted, and a capacitor 17 is inserted between the base of the transistor 11 and the collector of the transistor 10. The collectors of transistors 10 and 11 are resistors 12
And 13 are connected to the power supply terminal 14 respectively. A resistor 30 is inserted between the base of the transistor 11 and the power supply terminal 14. The synchronization signal Hs is supplied to the input terminal indicated by 18. This synchronizing signal Hs is supplied to the base of the transistor 11 as a trigger signal via the differentiating circuit 19 and the diode 20.
Mono-multi is triggered at the timing of the leading edge of the sync signal Hs. Output terminal 21 from collector of transistor 11
Is derived.

FIG. 3 shows the waveform of each part of the monomulti shown in FIG. 2, and FIG. 3A shows the synchronizing signal Hs. A negative differential pulse generated at the leading edge of the synchronizing signal Hs is supplied to the base of the transistor 11.

In a steady state, transistor 10 turns off and transistor 11
Is on and the output signal is at low level. When a negative differential pulse trigger input is applied, the base potential of the transistor 11 is lowered, the collector potential of the transistor 11 rises, and the transistor 10 turns on and the transistor 11 turns off in an instant. At this time, the voltage across capacitor 17 does not change, so when transistor 10 is off, + Vc
The potential at one end of the capacitor 17, which was c, is the transistor 10
For the 0 V during ON, drops from the potential of the other end of the capacitor 17 is V _BE (base-emitter voltage drop of transistor 11) until (V _BE -Vcc). After this, the capacitor
A current flows through the resistor 30 through the resistor 30, and the base voltage of the transistor 11 rises with a time constant determined by the capacitor 17 and the resistor 30. Then, the base voltage of the transistor 11 is V
_When it becomes larger than _BE , the transistor 11 turns on and the output falls. FIG. 3B shows the change in the base voltage of the transistor 11, and FIG. 3C shows the output signal.

The pulse width T of the output signal is determined by the capacitance C of the capacitor 17 and the value R of the resistor 30, regardless of the value of the power supply voltage + Vcc, and is about 0.7 RC [sec].

The frequency-voltage conversion circuit 7 is provided with the above-mentioned mono-multi, and the duty ratio of the output signal of the mono-multi changes with the frequency of the synchronization signal Hs. The output signal of this mono-multi is supplied to the integrating circuit, and from the integrating circuit,
The higher the frequency of the synchronization signal Hs, the larger the output voltage.
Vs is obtained. This output voltage Vs is supplied to the constant current circuit 8, and the constant current circuit 8 forms a constant current i corresponding to the output voltage Vs.

FIG. 4 shows an example of the configuration of the constant current circuit 8 and the monomulti 2. The constant current circuit 8 is provided with a PNP type transistor 22, and the emitter of the transistor 22 is connected via a resistor 23 to a terminal 24 to which the output voltage Vs is supplied. This terminal
24 is a resistor 25, a diode 26 and a variable resistor (volume) 2
Grounded via 7. The connection point of the diode 26 and the variable resistor 27 and the base of the transistor 22 are connected,
A capacitor 28 is inserted between this connection point and ground. A constant current i equal to the current flowing through the series circuit of the resistor 25, the diode 26 and the variable resistor 27 flows between the collector and the emitter of the transistor 22.

The mono-multi 2 is configured similarly to the mono-multi shown in FIG. However, the resistor 30 in FIG. 2 is not connected, but the connection point of the base of the transistor 11 and the capacitor 17 is connected to the collector of the transistor 22 of the constant current circuit 8. Therefore, the trigger pulse is supplied at the front edge of the input synchronization signal Hs shown in FIG. 5A, and the voltage change becomes linear after the base voltage of the transistor 11 drops by Vcc as shown in FIG. 5B. FIG. 5C shows the output signal output to the output terminal 21, and the pulse width of this output signal is the delay amount.
Td.

The voltage V at the connection point between the capacitor 17 and the base of the transistor 11 is: V = Q / C = (it) / C ... Substituting (V = Vcc, t = Td) into the equation, Td = (Vcc · C) / i… And the voltage drop in the diode 26 is Vf
If the resistance values of 23, 25 and variable resistance 27 are R23, R25 and R27, respectively, In the equation, (Vf = V _BE ), Here, if (Vs≫V _BE ), Also, since the voltage Vs is proportional to the frequency f of the input synchronization signal Hs, if the equation is rewritten using the constant k determined by the circuit, when (R23 = R25), Substituting the expression into the expression, finally Td is Becomes

By changing the resistance value R27 of the variable resistor 27,
The delay time Td is variable, and the image can be horizontally shifted on the screen. The value of the delay time Td is inversely proportional to the frequency f of the input synchronizing signal. On the other hand, the shift amount of the image with respect to the delay time Td increases in proportion to the frequency f.
Therefore, the shift amount of the image on the screen with respect to the change of the resistance value R27 becomes substantially constant regardless of the frequency f.

〔The invention's effect〕

According to the present invention, since the shift amount of the image on the screen is independent of the frequency of the input synchronizing signal, the relationship between the rotation amount of the adjustment podium and the shift amount is kept constant, and
When the position of the image is adjusted to the center with respect to the input synchronizing signal of a certain frequency, the image is positioned substantially in the center of the screen with respect to the input synchronizing signals of different frequencies.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, a connection diagram of an example of the mono-multi shown in FIGS. 2 and 3, and waveform diagrams of respective parts used for explaining the operation thereof, and FIGS. 4 and 5 are mono-multi and A connection diagram of the constant current circuit and waveform diagrams of respective parts used for explaining the operation thereof, and FIGS. 6 and 7 are waveform diagrams used for explaining the image shift operation when the frequencies of the input synchronizing signals are different. Description of main symbols in the drawing 1: Sync signal input terminal, 2, 3: Mono-multi, 7: Frequency voltage conversion circuit, 8: Constant current circuit.

Claims (1)

(57) [Claims] 1. A horizontal image shift circuit to which a horizontal synchronizing signal of two or more frequencies is supplied, a frequency voltage converting circuit for converting the frequency of an input synchronizing signal into a voltage, and an output voltage from the frequency voltage converting circuit. A constant current circuit for converting the constant current into a constant current, means for varying the constant current according to a horizontal shift amount, and a delay circuit for delaying the input synchronization signal for a time period according to the value of the constant current. A horizontal image shift circuit characterized by the above.