JPS6141337Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an electromagnetic deflection circuit for a display device or the like using a cathode ray tube.

In particular, the present invention relates to a device for automatically adjusting the vertical screen amplitude of this electromagnetic deflection circuit.

Generally, in display devices using cathode ray tubes, the deflection frequency is not as fixed as in well-known standard television receivers. This deflection frequency varies individually depending on the system in which the display device is used and can vary, for example, from 30 to 60 Hz. This deflection frequency is set to a value suitable for the system due to problems such as the number of displayed characters and screen flickering, and the synchronization pulse with this frequency is usually generated by a synchronization signal generator installed inside the display. ing.

By the way, in this type of display device, if the frequency of the synchronization pulse differs, the screen amplitude changes in inverse proportion to the frequency. Therefore, when mass-producing such a system with display devices each having a different deflection frequency, the factory must adjust the screen amplitude each time according to the frequency of the synchronization pulse, and this adjustment work is extremely complicated. .

This proposal has been made in view of the above, and provides an automatic vertical screen amplitude adjustment device that can automatically maintain the screen amplitude at a predetermined level even if the deflection frequency is changed depending on the system. be.

Furthermore, the present invention provides a device that can always obtain a stable vertical screen amplitude even if the oscillation frequency of the synchronization signal generator that generates the synchronization pulses is fluctuated due to external temperature changes. be.

The present invention will be explained below with reference to the drawings. FIG. 1 is a circuit connection diagram of an embodiment of the present invention, in which 1 is a vertical oscillation circuit, 2 is a sawtooth wave generation circuit, 3 is a vertical deflection drive circuit, 4 is a deflection yoke, and 5 is a phase inversion circuit. constitutes a well-known vertical electromagnetic deflection circuit. Further, 6 is a first circuit forming a DC regeneration circuit described later, 7 is a second circuit forming an amplitude detection circuit described later, 8 is a DC amplifier circuit, and 9 is supplied to the sawtooth wave generation circuit 2 described above. The third circuit controls the power generated, and these constitute the main part of the present invention.

First, the vertical oscillation circuit 1 corresponds to the synchronizing signal generator mentioned above, and a vertical synchronizing pulse is output from the output terminal 11. For convenience of explanation, it is assumed here that this vertical synchronizing pulse is a positive pulse that is repeatedly output as shown in FIG. 2A.
Therefore, this synchronizing pulse is input to the transistor 23 of the sawtooth wave generating circuit 2 via the capacitor _C1 . The switching operation of the transistor 23 is performed by a positive synchronizing pulse inputted to its base, and a negative synchronizing pulse of opposite polarity appears at its collector. At this time, the peak level during the period (vertical scanning period) in which there is no negative synchronizing pulse is determined by the control transistor 9 of the third circuit 9, which will be described later.
This value is almost the same as the emitter voltage V _S of 1. Further, a variable resistor 24 is connected to the collector of the transistor 23 as a load resistance, and a capacitor 25 is connected between the collector and ground.

As is well known, the variable resistor 24 and the capacitor 25 repeatedly charge and discharge the capacitor 25 in accordance with the switching operation of the transistor 23, and a sawtooth waveform voltage V _C for deflection is drawn from both ends of the capacitor 25. Therefore, variable resistor 2
4 and the capacitor 25 form a charging/discharging circuit, and the slope of the sawtooth waveform is determined by the time constant determined by the product of the two, as is well known. Further, the peak value of the sawtooth waveform voltage V _C is set in advance by adjusting the variable resistor 24 so as to obtain a desired screen amplitude. The sawtooth waveform voltage V _C is applied to the next stage vertical deflection drive circuit 3 and drives the deflection yoke 4 as is well known.

By the way, if the time constant of the charging/discharging circuit is constant at a preset value as mentioned above,
The peak value of the voltage V _C of the sawtooth waveform is changed in inverse proportion to the frequency of the synchronizing pulse that switches the transistor 23 . On the other hand, as is well known, this peak value is changed in proportion to the charging supply voltage applied to the charging/discharging circuit, in other words, in this case, in proportion to the emitter voltage V _S of the control transistor 91.

This proposal focuses on the fact that the peak value of the voltage V _C of the sawtooth waveform can be changed by the supply voltage V _S , and after setting the time constant of the charging/discharging circuit in advance to correspond to the desired screen amplitude, no changes can be made. In order to maintain the voltage V _C peak value of the sawtooth waveform that always obtains this screen amplitude without changing, the fluctuation in the peak value due to the frequency change of the synchronization pulse is corrected so that it becomes constant by adjusting the supply voltage. It is something.

Hereinafter, the main circuit operation for performing such an operation of the present invention will be explained.

First, the positive synchronizing pulse of the vertical oscillation circuit 1 shown in FIG. 2A is inverted by the well-known phase inversion circuit 5 into a negative synchronizing pulse, that is, a first pulse signal, as shown in FIG. This first pulse signal is input to the first circuit 6 via a capacitor C. 1st
The circuit 6 is a DC regeneration circuit composed of a well-known phase inversion type operational amplifier 65, a diode 63, and resistors 61, 62, and 64. Therefore, the DC component is cut off, and an AC signal having a waveform as shown in FIG. At the same time, the DC component E fed back from the output side via the resistor 64 is input to the terminal as shown by the broken line in FIG. 2B. The position of the first pulse signal superimposed on this DC component E moves up and down depending on the frequency. That is, when the frequency of the first pulse signal is high, the duty of the first pulse signal increases, so it moves upward, and when the frequency is low, the duty of the first pulse signal decreases, so it moves downward. On the other hand, since the terminal is grounded through the diode 63, it has a reference level equal to the voltage drop V _O of the diode 63. During the input period of the first pulse, the operational amplifier 65 sends out an inverted output of a predetermined high voltage (for example, +12V) for all portions whose peak value is less than V _O , and during the period when the first pulse is not input (scanning period), it sends out an inverted output whose voltage drops according to the frequency.
Therefore, when the first pulse signal is input to the operational amplifier 65, its output is proportional to the frequency of the first pulse signal, i.e., a positive synchronous pulse with an alternating current amplitude V _P , i.e., a sawtooth wave generating circuit. A second pulse signal having the same phase as the synchronization pulse injected into the second pulse is output.

This now means that the deflection frequency of the positive sync pulse is
₂ becomes higher than the deflection frequency ₁ , the interval between adjacent pulses of the first pulse signal output from the phase inversion circuit 5 becomes shorter, and correspondingly, the above-mentioned DC component E applied to the terminal of the operational amplifier 65 becomes shorter. The position relative to the position will rise as shown by arrow f ₁ in Figure 2 (b). At this time, the AC amplitude V _P of the output of the operational amplifier 65 is increased as shown by the arrow f ₁ in FIG. 2C.

Conversely, when the deflection frequency ₁ changes to a lower deflection frequency ₂ , the interval between adjacent pulses of the first pulse signal becomes longer. Descend as shown by arrow _f2 in Figure B. As a result, the AC amplitude V _P of the output of the operational amplifier 65 is reduced as shown by the arrow f ₂ in FIG. 2C.

This means that the position on the negative side of the first pulse signal with respect to the above-mentioned DC component E input to the terminal of the operational amplifier 65 is inversely proportional to the deflection frequency, proportional to the interval between adjacent pulses, and is output. Second
This means that the alternating current amplitude V _P of the pulse signal is proportional to the deflection frequency and inversely proportional to the interval between adjacent pulses.

The second pulse signal having such an AC amplitude V _P is input from the first circuit 6 to the second circuit 7 at the next stage. The second circuit 7 includes a diode 71 and a resistor 7
2, 74, and a capacitor 73 constitute a well-known amplitude detection circuit. This second circuit 7 generates a DC voltage signal across a resistor 74 at a DC level corresponding to the AC amplitude V _P of the input second pulse signal.

This DC voltage signal is input to the DC amplifier circuit 8 at the next stage. The DC amplifier circuit 8 is composed of an operational amplifier 85 and resistors 81, 82, 83, and 84.
The operational amplifier 85 receives the above-mentioned DC voltage signal from the resistor 81.
is input to the terminal via. Therefore, the output is not inverted, and the operational amplifier 85 outputs the amplified DC level change of the input DC voltage signal.

The output of such a DC amplifier circuit 8 is the third stage of the next stage.
The signal is input to the circuit 9. The third circuit 9 includes a control transistor 91, bias resistors 92, 93,
94, and the output of the above-mentioned DC amplifier circuit 8, that is, the DC voltage signal, is transmitted through bias resistors 92 and 93.
is applied to the connection point. Further, the control transistor 91 has its collector and emitter connected between the variable resistor 24 of the sawtooth wave generation circuit 2 and the power supply +B, and receives DC power for charging supplied to the sawtooth wave generation circuit 2. Adjust. This results in adjusting the charging supply voltage V _S of the charging/discharging circuit of the sawtooth wave generating circuit 2. This adjustment is controlled by adjusting the bias of the control transistor 91. The bias of the control transistor 91 is the resistor 9.
It is adjusted by the DC voltage signal from the previous stage applied to the connection point between 2 and 93.

In other words, if the deflection frequency of the synchronizing pulse output from the vertical oscillation circuit 1 is now shifted higher to frequency ₁ , the DC level of the DC voltage signal output from the second circuit 7 will be: Rise. Therefore, this variation is amplified by the DC amplifier circuit 8 and the resistors 92 and 9 of the third circuit 9
Increase the potential at the connection point 3. As a result, the bias of the control transistor 91 becomes deeper, and the charging supply voltage V of the charging/discharging circuit of the sawtooth wave generating circuit 2 becomes deeper.
Increase _S.

At this time, the transistor 23 of the sawtooth wave generating circuit 2 is switched by the deflection frequency moving higher than the frequency ₁ , so if the charging supply voltage V _S is constant, the peak value of the sawtooth waveform voltage V _C created by the charging and discharging circuit will tend to move downward as already mentioned. However, since the charging supply voltage V _S rises at this time as described above, the peak value of the sawtooth waveform voltage V _C is maintained constant. Therefore, the phase inverter circuit 5, the first circuit 6, the second circuit 7, the DC amplifier circuit 8, and the third circuit are designed to respond linearly to changes in the deflection frequency,
Furthermore, the increase in the supply voltage V _S for charging is designed to correspond to the decrease in the voltage V _C of the sawtooth waveform so that the peak value of the voltage V C is constant.

As above, we have explained the operation of each part when the deflection frequency moves in the direction of high frequency ₁ , but when the deflection frequency moves in the direction of low frequency ₂ , the operation is completely opposite to the above-mentioned operation. .

As a result, the peak value of the sawtooth waveform voltage V _C is always maintained constant even if the deflection frequency changes, as shown in FIG. 2D.

As described above, the present invention has a sawtooth that controls the vertical amplitude of the screen even if the oscillation frequency of the vertical oscillation circuit 1, that is, the synchronizing signal generator, is actively changed or fluctuates due to external temperature changes. The peak value of the voltage V _C of the waveform can be maintained constant at all times.

In the embodiment device, a DC regeneration circuit using a phase inversion type operational amplifier 65 was used as an example of the first circuit, but the present invention is not limited to this, and other circuit means may be used. The inverting circuit 5 may be included in this circuit. In addition, vertical oscillation circuit 1
It is sufficient that the synchronization pulses given to the sawtooth wave generation circuit 2 and the second circuit 6 are in an antiphase relationship with each other, and the above-mentioned phase inverter circuit 5 is built in to output two synchronization pulses of antiphase. It may be composed of things. Of course, the second circuit 7 and the third circuit 9 are not limited to those of the embodiment device, and can be realized by other circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit wiring diagram showing an embodiment of the present invention;
FIG. 2 shows a waveform diagram of the main part of the circuit connection diagram of FIG. 1. 24, 25... Charge/discharge circuit, 5... Phase inversion circuit, 6... First circuit, 7... Second circuit, 9...
...Third circuit, 8...DC amplifier circuit.

Claims (1)

[Claims for Utility Model Registration] In an electrode deflection circuit that creates a sawtooth waveform voltage based on a vertical synchronization pulse in a charging/discharging circuit including a capacitor and a resistor in order to cause a sawtooth waveform current to flow through the deflection yoke, the vertical in response to a first pulse signal in antiphase with the synchronization pulse, the alternating current amplitude decreases by increasing the spacing between adjacent pulses of the first pulse signal; a first circuit that generates a second pulse signal that is in phase with the vertical synchronization pulse whose AC amplitude increases; a second circuit that outputs a DC voltage signal that corresponds to the AC amplitude of the second pulse signal; A third control unit that controls the value of the supply voltage for charging applied to the charging/discharging circuit so as to keep the peak value of the voltage of the sawtooth waveform constant in response to the DC voltage signal.
An automatic vertical screen amplitude adjustment device characterized by comprising a circuit.