JPS6141338Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a deflection circuit for a display device or the like using a cathode ray tube.

In particular, the present invention relates to an automatic adjustment device for the vertical screen amplitude of this deflection circuit.

Generally, in display devices using cathode ray tubes, the deflection frequency is not as fixed as in well-known standard television receivers. This deflection frequency varies individually depending on the system in which the display device is used and can vary, for example, from 30 to 60 Hz. This deflection frequency is set to a value suitable for the system due to problems such as the number of displayed characters and screen flickering, and the synchronization pulse with this frequency is usually generated by a synchronization signal generator installed inside the display. ing.

By the way, in this type of display device, if the frequency of the synchronization pulse differs, the screen amplitude changes in inverse proportion to the frequency. Therefore, when mass-producing display devices with different deflection frequencies for each of these systems, the factory must adjust the screen amplitude each time according to the frequency of the synchronization pulse, and this adjustment work is extremely complicated. .

This proposal has been made in view of the above, and provides an automatic vertical screen amplitude adjustment device that can automatically maintain the screen amplitude at a predetermined level even if the deflection frequency is changed depending on the system. be.

Furthermore, the present invention provides a device that can always obtain a stable vertical screen amplitude even if the oscillation frequency of the synchronization signal generator that generates the synchronization pulses is fluctuated due to external temperature changes. be.

The present invention will be explained below with reference to the drawings. Figure 1 is a circuit connection diagram of an embodiment of the present invention, in which 1 is a vertical oscillation circuit, 2 is a sawtooth wave generation circuit, 3 is a vertical deflection output circuit, 4 is a deflection yoke, and 5 is a buffer amplifier circuit. constitutes a well-known vertical electromagnetic deflection circuit. Further, 6 is a first circuit that generates a first pulse signal (described later), 7 is an amplitude detection circuit, 8 is a DC amplification circuit, and 9 is a second circuit for generating a sawtooth wave generation circuit 2 (described later).
The third circuit supplies the pulse signal, and these constitute the main part of the present invention.

First, the vertical oscillation circuit 1 corresponds to the synchronizing signal generator mentioned above, and a vertical synchronizing pulse is output from the output terminal 11. For convenience of explanation, it is assumed here that this vertical synchronizing pulse is a negative pulse that is repeatedly output. Therefore, this synchronizing pulse is input to the transistor 51 of the buffer amplifier circuit 5 via the capacitor _C1 . This transistor 5
The negative synchronizing pulse input to the circuit 1 is inverted via a third circuit 9 and an inverting circuit 10, which will be described later, and is input to the base of the transistor 23 of the sawtooth wave generating circuit 2 as a positive synchronizing pulse. Transistor 23 thereby undergoes a switching action, and a negative synchronizing pulse of opposite polarity appears at its collector. A variable resistor 24 is connected to the collector of the transistor 23 as a load resistance, and a capacitor 25 is connected between the collector and ground.

As is well known, the variable resistor 24 and the capacitor 25 repeatedly charge and discharge the capacitor 25 as the transistor 23 switches, and a sawtooth waveform voltage V _C for deflection is drawn from both ends of the capacitor 25. . Therefore, the variable resistor 24 and the capacitor 25 form a charging/discharging circuit, and the slope of the sawtooth waveform is determined by the time constant determined by the product of the two, as is well known. Also, the sawtooth waveform voltage V _C
The peak value of is set in advance by adjusting the variable resistor 24 so as to obtain a desired screen amplitude. The sawtooth waveform voltage V _C is applied to the next stage vertical deflection output circuit 3, and drives the deflection yoke 4 as is well known.

By the way, if the time constant of the charging/discharging circuit is constant at a preset value as mentioned above, the peak value of the voltage V _C of the sawtooth waveform is the voltage of transistor 2.
3 is changed in inverse proportion to the frequency of the synchronizing pulse that causes the switching operation.

Therefore, in the present invention, after setting the time constant of the charging/discharging circuit in advance to correspond to the desired screen amplitude, the peak value of the voltage V _C of the sawtooth waveform that obtains this screen amplitude is always maintained without making any changes. The transistor 23 of the sawtooth wave generating circuit 2
The variation in the peak value due to the frequency change of the synchronizing pulse applied to the synchronous pulse is controlled in inverse proportion to this frequency change, so that it is corrected to be constant.

Hereinafter, the main circuit operation for performing such an operation of the present invention will be explained.

First, the negative synchronizing pulse of the vertical oscillation circuit 1 is input to the first circuit 6 via the capacitor _C2 . The first circuit 6 is a well-known phase inversion operational amplifier 65.
, a diode 63, and resistors 61, 62, and 64.The DC component of the input negative synchronizing pulse is cut off by the capacitor _C2 , resulting in a waveform as shown in Figure 2A. An alternating current signal is injected into the terminals of operational amplifier 65. At the same time, a resistor 64 is connected to the terminal as shown by the broken line in Fig. 2A.
A direct current component E fed back from the output side is inputted via. The position of the first pulse signal superimposed on this DC component E moves up and down depending on the frequency.
That is, when the frequency of the first pulse signal is high, the duty of the first pulse signal increases, so it moves upward, and when the frequency is low, the duty of the first pulse signal decreases, so it moves downward. On the other hand, since the terminal is grounded through the diode 63, it has a reference level equal to the voltage drop V _O of the diode 63. During the input period of the first pulse, the operational amplifier 65 has a peak value of V _O
All voltages below are set to a predetermined high voltage (e.g. +
12V), and during a period (scanning period) in which the first pulse is not input, an inverted output whose voltage drops according to the frequency is sent out. Therefore, when the first pulse signal is input to the operational amplifier 65, its output is proportional to the frequency of the first pulse signal, i.e., a positive synchronous pulse with an alternating current amplitude V _P , i.e., a sawtooth wave generating circuit. A second pulse signal having the same phase as the synchronization pulse injected into the second pulse is output.

This now means that the deflection frequency of the negative sync pulse is
₂ becomes higher than the deflection frequency ₁ , the interval between adjacent negative synchronizing pulses becomes shorter, and correspondingly, the position with respect to the above-mentioned DC component E applied to the terminal of the operational amplifier 65 is as shown by the arrow in FIG. 2A. It will rise as shown in ₁ . At this time, the AC amplitude V _P of the output of the operational amplifier 65 is increased as shown by arrow ₁ in FIG.

Conversely, if the deflection frequency ₁ changes to a lower deflection frequency ₂ , the interval between adjacent negative synchronizing pulses becomes longer. A arrow
Descend as shown in ₂ . As a result, the AC amplitude V _P of the output of the operational amplifier 65 is reduced as shown by arrow ₂ in FIG.

This means that the position on the negative side of the first pulse signal with respect to the above-mentioned DC component E input to the terminal of the operational amplifier 65 is inversely proportional to the deflection frequency, proportional to the interval between adjacent pulses, and is output. Second
This means that the alternating current amplitude V _P of the pulse signal is proportional to the deflection frequency and inversely proportional to the interval between adjacent pulses.

The first pulse signal having such an AC amplitude V _P is input from the first circuit 6 to the amplitude detection circuit 7 at the next stage. This amplitude detection circuit 7 includes a diode 71,
It is composed of well-known resistors 72 and 74 and a capacitor 73. The amplitude detection circuit 7 generates a DC voltage signal across the resistor 74 at a DC level corresponding to the AC amplitude V _P of the input first pulse signal.

This DC voltage signal is input to the DC amplifier circuit 8 at the next stage. The DC amplifier circuit 8 is a well-known operational amplifier 8.
5 and resistors 81, 82, 83, and 84. The above-mentioned DC voltage signal is input to the terminal of the operational amplifier 85 via the resistor 81. Therefore, the output is not inverted, and the operational amplifier 85 outputs the amplified DC level change of the input DC voltage signal.

Therefore, the amplitude detection circuit 7 and the DC amplifier circuit 8 form a second circuit having a DC level proportional to the AC amplitude V _P of the first pulse signal.

The output of such a DC amplifier circuit 8 is the third stage of the next stage.
The signal is input to the circuit 9. As already mentioned, this third circuit 9 receives the negative synchronizing pulse from the buffer amplifier circuit 5 at the previous stage. and,
This third circuit 9 includes a diode 91 for DC clamping and a diode 92 for isolation.
and a slice circuit formed by resistors 93, 94, 95 and 96. Therefore, the negative synchronizing pulse signal inputted from the buffer amplifier circuit 5 in the previous stage is clamped to a constant DC level V _d by the diode 91 as shown in FIG. 2C. On the other hand, the slice circuit formed by the resistors 93 to 95 divides the power supply voltage applied to the terminal +B appropriately, and also injects the DC voltage signal from the DC amplifier circuit 8 already mentioned into the connection point between the resistors 94 and 95. It is something that will be done. As a result, the above-mentioned DC clamped negative synchronization pulse is sliced based on the DC clamp level V _d depending on the DC level of the DC voltage signal injected to the connection point between the resistors 94 and 95. This slice level V _S is
Since the DC voltage signal has a DC level proportional to the AC amplitude V _P of the first pulse signal as described above, it consequently changes in accordance with the change in the AC amplitude V _P of the first pulse signal. _2D and 2E show such a state, in which the negative synchronizing pulse shown in FIG. If the frequency changes in _one direction, the second
As shown in FIG. 2, it is sliced by the slice level V _S2 , and when it changes to _two lower directions, it is sliced by the slice level V _S1 as shown in FIG. 2 E. Here, for convenience, such a clan and sliced negative synchronization pulse will be referred to as a second pulse signal. The sawtooth wave generating circuit 2 receives an inverted signal (positive pulse signal) based on the second pulse signal via the inverting circuit 10 . On the other hand, when the inverted signal is superimposed on the base voltage of the transistor 23, the amplitude of the inverted signal increases as the frequency increases, and the collector voltage required to lower the base voltage is high, in this case capacitor 25
A large current flows through the capacitor 25, and the capacitor 25 is rapidly charged. Further, as the frequency decreases, the amplitude of the inverted signal becomes smaller, causing the base voltage to rise, and the collector voltage to fall accordingly, a small current flows through the capacitor 25, and the capacitor 25 is charged at a low speed.

As a result, the peak value of the sawtooth waveform voltage V _C is always maintained constant even if the deflection frequency changes, as shown in FIG.

As described above, the present invention provides a sawtooth control that controls the vertical amplitude of the screen even if the oscillation frequency of the vertical oscillation circuit 1, that is, the synchronizing signal generator, is actively changed or fluctuates due to external temperature changes. The peak value of the voltage V _C of the waveform can always be maintained constant.

[Brief explanation of the drawing]

FIG. 1 is a circuit wiring diagram showing an embodiment of the present invention;
FIG. 2 shows waveforms of essential parts of the circuit connection diagram of FIG. 1. 1... Oscillation circuit, 6, 7... First circuit, 7,
8...Second circuit, 9...Third circuit, 2, 3...
...Fourth circuit.

Claims (1)

[Claims for Utility Model Registration] An oscillator circuit that outputs a vertical synchronization pulse; a first circuit that generates a first pulse signal having an opposite phase to the vertical synchronization pulse whose alternating current amplitude increases as the interval decreases; and a direct current having a direct current level proportional to the alternating current amplitude of the first pulse signal. a second circuit that outputs a voltage signal; and clamping the vertical synchronization pulse output from the oscillation circuit at a predetermined DC level and slicing it in accordance with the DC level supplied from the second circuit. a third circuit that outputs a second output pulse signal by inputting the second pulse signal and outputting a current proportional to the amplitude of the second pulse signal during a period in which the second pulse signal is not present; a fourth circuit that generates a sawtooth wave voltage in a charge/discharge circuit that charges the capacitor and discharges the capacitor during the period when the second pulse signal is present, and causes a sawtooth waveform current to flow through the deflection yoke; A vertical deflection circuit characterized by comprising: