JPH0646779B2 - Vertical deflection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a vertical deflection circuit for a devisioning receiver.

(B) Prior art FIG. 5 is a block diagram showing a vertical deflection circuit.
Is a sync separation circuit, and (2) is an integration circuit. Reference numeral (3) is a vertical oscillating section, which comprises a vertical oscillating circuit (4) and a sawtooth wave generating circuit (5). Reference numeral (6) is a vertical deflection output section, which comprises a drive circuit (7) and a vertical output circuit (8).

In such a circuit, the sync separation circuit (1) and the integration circuit (2)
Vertical oscillation circuit by vertical synchronization signal shaped through (4)
Oscillate synchronously, the oscillation output pulse of the oscillation circuit (4) is shaped into a sawtooth wave by the sawtooth wave generation circuit (5), amplified by the drive circuit (7), and then the vertical output circuit (8) Supply to. In such a vertical deflection circuit, the retrace pulse width of the vertical deflection output is from the oscillation circuit (4) to the vertical output circuit (8).
It is affected by the pulse width of the drive signal supplied to the. In particular, in a so-called OTL type vertical deflection output circuit that does not use a vertical output transformer, since there is no large inductance element such as a vertical output transformer that limits the return width by itself in the circuit, the blanking period of the vertical deflection output is It is almost uniquely determined by the pulse width of the drive signal to the output circuit (8).

By the way, in the vertical oscillation circuit (4), the rise of the oscillation output is determined by the vertical synchronization signal applied to the oscillation circuit (4), so the rise time of oscillation can be accurately specified. However, the falling edge of the oscillation output pulse, that is, the end time of the pulse, is determined only by the operating conditions of the oscillation circuit itself, so it is extremely affected by the electrical components used and the external connection circuit due to the nature of the oscillator. Therefore, when the oscillation pulse falls, that is, when the pulse ends, the pulse width of the oscillation pulse tends to be extremely unstable. The instability of the pulse width of the oscillation output causes the instability of the output circuit.

For this reason, in Japanese Patent Publication No. 55-12784,
As shown in the block diagram of FIG. 6, in which the same parts as those of FIG. 5 are designated by the same reference numerals, the vertical oscillation circuit (4) and the vertical output circuit (8)
A pulse width control circuit (9) controlled by the output of the vertical output circuit (8) is provided between the vertical output circuit (8) and a pulse having a predetermined pulse width is generated by the pulse width control circuit (9). I am trying to supply it to.

FIG. 7 is a circuit diagram showing in detail the essential parts of the pulse width control circuit (9) of the vertical oscillation circuit, and FIG. 8 is a waveform diagram for explaining the operation thereof, and FIG. An oscillation output pulse as shown in a) is supplied to the base of the switching transistor (Tr1) in the pulse width control circuit (9) to turn on / off the transistor (Tr1). The charge / discharge capacitor (C1) is charged through the constant current resistor (R0) and the sawtooth wave time constant resistor (R1) when the transistor (Tr1) is off, and the capacitor (C1) is turned on when the transistor (Tr1) is on. The charge of C1) is discharged through the path of the collector / emitter of the transistor. As a result, a sawtooth wave voltage as shown by the solid line in FIG. 8 (b) is generated across the capacitor (C1). This sawtooth wave voltage is supplied to the differential amplifier composed of the transistors (Tr2) and (Tr3), but the base voltage level (E0) of the transistor (Tr3).
Since the slice level of the sawtooth voltage supplied to the base of the transistor (Tr2) is fixed by, the collector of the transistor (Tr2) outputs a square wave as shown by the solid line in Fig. 8 (c). A pulse is obtained. This output square wave pulse is amplified and phase-inverted by the transistor (Tr4), and is supplied to the base of the transistor (Tr5) with a waveform as shown in FIG. 8 (d) at the point (D), and its output is further supplied to the transistor (Tr7). ) Supply to the base. On the other hand, the input terminal is connected to the base (point E) of the transistor (Tr6).
The oscillation output pulse as shown in FIG. 8 (e) similar to that of (A) is supplied. Therefore, the transistor (Tr5) (Tr6)
Since the AND gate circuit is composed of (Tr7), the collector (F) of the transistor (Tr7) is shown in FIG.
An output waveform is obtained by inverting the one shown by the solid line in FIG. 8 (f) from which the solid line waveform in FIG. 8 (d) is subtracted. This square wave pulse is supplied to the vertical output circuit (8) via the sawtooth wave generation circuit (5) and the drive circuit (7), and this output circuit (8)
The vertical deflection output voltage waveform at point (G) is as shown by the solid line in FIG. 8 (g). The vertical deflection output voltage as shown in FIG. 8 (g) is smoothed by an integrator circuit (10) consisting of a resistor (R2) and a capacitor (C2), divided into an appropriate size, and a pulse width control voltage ( E1) is supplied to one end of the constant current resistor (R0).

Now, it is assumed that the output retrace pulse width (Tr) of the vertical output circuit (8) becomes narrow and becomes (Tr '). Then, the voltage (Vr) of the pulse portion increases (Vr '), but the upper end (c) of the pulse portion is fixed by the DC power supply voltage (Vb2) of the vertical output circuit (8), so that the output The average DC level (Vm) becomes low and becomes (V'm).
Therefore, the pulse width control voltage (E1) supplied to one end of the constant current resistor (R0) becomes low, and the charging voltage of the charging / discharging capacitor (C1) becomes low, so that the voltage between both ends of the capacitor (C1) rises first. As shown by the broken line in Fig. 8 (b), it becomes loose and gentle.

Therefore, the waveforms at points (C) and (D) in Fig. 7 are shown in Fig. 8 (c).
It becomes narrower as shown by the broken line in (d). As a result, the output square wave pulse at point (F) of the pulse width control circuit (9) is shown in Fig. 8.
It becomes wider as shown by the broken line in (f), and the narrow output retrace pulse width (Tr ') is corrected to an appropriate pulse width (Tr). Further, it can be easily understood that even when the vertical blanking pulse width is widened, the pulse width is corrected to an appropriate pulse width by the action opposite to the above.

As described above, the pulse width control circuit is controlled by the vertical output voltage so that the average DC level (Vm) of the vertical output and the retrace pulse width of the output are substantially optimized. Even if the pulse width fluctuates to some extent, it makes no difference.

FIG. 9 shows a conventional example of a conventional vertical deflection circuit to which the pulse width control circuit (9 ') described above is added, and FIG. 10 shows a waveform diagram for explaining its operation.
A pulse (P0) as shown in FIG. 10 (a) is output from (9 '), and the switching transistor (Q1) is driven by the pulse (P0). Therefore, the sawtooth wave generation circuit
The charge / discharge capacitor (C3) for forming the sawtooth wave of (15) flows from the power supply terminal (+ B1) through the resistors (R3) and (R4) in the scanning period (Ts) [see FIG. 10 (a)]. The capacitor (C3) is charged by the charging current (iC), and the switching transistor (Q1) is turned on by the pulse (P0) during the blanking period (TR).
The electric charge charged in the capacitor is discharged by the resistor (R4) and the discharge current (iD) flowing through the collector-emitter path of the transistor (Q1). As a result, the voltage across the capacitor (C3) becomes as shown in FIG. 10 (B), and the collector [(H) of the switching transistor (Q1) is shown.
Point], a voltage as shown in FIG. The voltage generated at the point (H) is amplified by the drive circuit (14) including the differential amplifier (11) and the drive transistor (Q2), and the vertical output circuit (12) including the transistors (Q3) and (Q4) is provided. ). Then, the vertical deflection coil (L) is generated by the vertical output voltage output from the vertical output circuit (12).
Is driven. Then, a sawtooth wave voltage as shown in FIG. 10 (c) is generated in the small resistor (R5) connected between the capacitor (C4) and the ground, and the sawtooth wave voltage is variable for vertical amplitude adjustment. Capacitor (C3) via resistor (VR)
A Miller integrator circuit is constructed by being introduced as negative feedback to one end of the above, and thereby a voltage having a good linearity is obtained as shown in FIG. In this circuit, the parabolic voltage (P1) generated in the vertical deflection coil (L) is applied to the waveform shaping circuit (13) and the pulse width control circuit (9 ').
In the discharge switching circuit in the above, the sawtooth wave voltage (P2) as shown in FIG. 10 (b) in which the peak value changes according to the average DC level of the parabola voltage (P1) is used. (P2) in the pulse width control circuit (9 ')
Although the pulse width control method described in the above publication is different in that the desired pulse width is obtained by slicing at a certain fixed level, the essential operation is the same, so here I will not go into detail.

By the way, as described above, in the pulse width control circuit (9 '), the vertical output voltage is shaped by the waveform shaping circuit (13), so that the sawtooth wave voltage (P0) as shown in FIG. ) Is created and the pulse width (TR) is determined by slicing at a constant level (E0), but a horizontal pulse component (P3) such as a flyback pulse is superimposed on the sawtooth wave voltage (P2), When the horizontal pulse component (P3) reaches the fixed slice level (E0), the slicing position changes, and the trailing edge of the pulse is the 11th.
It is shaken as shown by the broken line in the figure (b). When the pulse width fluctuates in this way, the voltage at each point fluctuates as shown in FIGS. 11 (c), (d), (e), and (f), resulting in the inconvenience that the vertical interlacing is not normally performed. The cause of the horizontal pulse component as described above being superimposed on the sawtooth wave as shown in FIG. 11 (a) is that the pulse width control circuit formed inside the IC causes the pulse width to be adjusted by the waveform shaping circuit (13) outside the IC. This is especially likely to occur when a sawtooth wave for control is created and supplied.

(C) Problems to be Solved by the Invention As described above, the present invention has an adverse effect on the screen due to the superposition of noise components such as horizontal pulse components on the sawtooth wave voltage used for the control operation of the pulse width control circuit. It is something to be removed.

(D) Means for Solving the Problems In order to solve the above problems, the present invention provides a sawtooth wave generating circuit between a vertical output circuit and a sawtooth wave generating circuit according to the magnitude of a deflection current. A current control circuit for controlling the current supplied to the charging / discharging capacitor is provided.

(E) Operation As described above, the current control circuit that controls the current supplied to the charging / discharging capacitor of the sawtooth wave generation circuit according to the magnitude of the deflection current is provided, so the oscillation output from the pulse width control circuit Even if the pulse width fluctuates, a predetermined sawtooth voltage can be obtained.

(F) Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 4, but in FIG. 1, FIG. 3 and FIG.
The same parts as those in the figure are designated by the same reference numerals.

That is, in the first embodiment of the present invention shown in FIG. 1, a resistor (R6) and a resistor (R7) are provided between the power supply terminal (+ B1) and the connection point of the capacitor (C4) and the small resistor (R5). )
And a parallel circuit of a capacitor (C5) are connected in series, and a diode (D0 with a polarity shown in the drawing is provided between the connection point of the resistor (R4) and the capacitor (C3) and the connection point of the resistor (R6) and the resistor (R7). ) Is connected to form a current control circuit (16). In this embodiment, an IC manufactured by Mitsubishi Electric Corp. (product number M51308SP) is used, and a pulse width control circuit (9 '), a switching transistor (Q1), and a resistor (R8) (IC) are used in the IC. Differential amplifier including R9)
(11) is configured, the output end of the waveform shaping circuit (13) is connected to the No. pin of the IC, the output end of the differential amplifier (11) is connected to the No. pin, and the switching transistor (Q1). The collector of is connected to pin number.

Next, the circuit operation of FIG. 1 will be described with reference to the waveform chart of FIG.

That is, at point (I), a sawtooth wave voltage having a magnitude proportional to the vertical deflection current flowing in the vertical deflection coil (L) as shown by the solid line in FIG. 2 (d) is generated. C
5), the voltage is raised to a level (E1) [VR, R5 << R6, R7] that is substantially determined by the voltage division ratio of the resistance (R6) and the resistance (R7), and the voltage as shown by the solid line in FIG. It occurs at point (K). Therefore, when the voltage value of the sawtooth wave voltage generated at the point (K) becomes equal to or higher than the forward rising voltage (VF) of the diode as compared with the voltage at the point (L), the diode (D0) becomes conductive and the capacitor (C3) Since the charging current (ie) for charging the capacitor flows, the charging current (ie) of the capacitor (C3) changes due to the voltage change at the point (K).

Now, for example, as shown in FIG. 2 (a), the horizontal pulse component (P2) is added to the sawtooth wave (P2) waveform-shaped by the waveform shaping circuit (13).
3) is superposed and the slice level (E0) is present on this pulse component (P3), the pulse (P0) supplied from the pulse width control circuit (13) to the base of the transistor (Q1).
The width of the capacitor also becomes narrower as shown by the broken line in Fig. 2 (b). Therefore, the voltage across the capacitor (C3) [Fig. 2 (c)] also rises as shown by the broken line, and The voltage also rises as shown by the broken line. As a result, the vertical output voltage at point (J) is shown in Fig. 2 (f).
It goes down as shown by the broken line, but at this time earth → resistance (R
5) → Capacitor (C4) → Vertical deflection coil (L) → Current flows momentarily in the path between the emitter and collector of the transistor (Q4). Therefore, the voltage at the point (K) drops to (E2) as shown in FIG. 2 (g), and the sawtooth wave voltage introduced to the point (K) also drops as shown by the broken line. On the other hand, the voltage at the (L) point when looking at the positive side of the capacitor (C3) from the ground is as shown in Fig. 2 (H), and the voltage at this (L) point and the voltage at the (K) point are The relationship is as shown in Fig. 2 (li).

Therefore, when the sawtooth voltage shown by the broken line in FIG. 2 (i) decreases, the conduction period of the diode (D0) becomes short and the charging current (ie) for charging the capacitor (C3) decreases. As a result, the voltage (Vc) across the capacitor (C3) decreases, and the voltage at the point (H) decreases, so that the vertical output voltage at the point (J) returns to the normal state.
In addition, FIG. 2 (nu) is the vertical blanking pulse width (TR ') of FIG.
2 shows a pulse having a pulse width corresponding to
Shows the amount of the charging current (ie), and FIG. 8 (e) shows the change in the voltage (Vc) across the capacitor (C3) accompanying the change in the charging current (ie).

In the above description, the case where the width of the pulse (P0) is narrowed has been described, but when the width of the pulse (P0) is widened by superimposing the horizontal pulse component of the opposite polarity on the sawtooth wave (P2). It will be easily understood that is corrected by the action opposite to the above as shown by the alternate long and short dash line in each waveform of FIG.

In the embodiment of FIG. 3, the cathode of the diode (D0) is connected to the connection point of the resistor (R3) and the resistor (R4), and in the embodiment of FIG. 4, the resistor (R4) and the capacitor (C) of FIG.
Although the connection position of 3) is reversed, the operation in these other embodiments is also similar to that of the above embodiment, and the description thereof is omitted.

(G) Effect of the Invention As described above, according to the present invention, even if a noise component such as a horizontal pulse component is superimposed on the sawtooth wave voltage used for the control operation of the pulse width control circuit, the vertical interlace There is an effect that adverse effects such as disorder can be eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the vertical deflection circuit of the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIGS. 3 and 4 are circuit diagrams showing other embodiments of the present invention. Is. Fifth
FIG. 6 is a block diagram of a vertical deflection circuit, FIG. 6 is a block diagram of a vertical deflection circuit having a pulse width control circuit, FIG. 7 is a block diagram showing details of the pulse width control circuit, and FIG. 8 is its operation explanation waveform. FIG. 9 is a diagram showing a conventional vertical deflection circuit having a pulse width control circuit, and FIGS. 10 and 11 are waveform diagrams for explaining the operation thereof. (4) …… Vertical oscillation circuit, (9 ′) …… Pulse width control circuit, (1
2) …… Vertical output circuit, (15) …… Sawtooth wave generation circuit, (16)
...... Current control circuit.

Claims (1)

[Claims] 1. Between the sawtooth wave generating circuit and the vertical oscillating circuit provided in the preceding stage of the vertical output circuit, the sawtooth wave is generated from the vertical oscillating circuit according to the average DC level of the vertical output voltage appearing in the vertical output circuit. In a vertical deflection circuit, a pulse width control circuit for variably controlling the pulse width of a vertical oscillation pulse supplied to a sawtooth wave generation circuit is provided, and an output pulse of the pulse width control circuit is supplied to the sawtooth wave generation circuit. A first feedback circuit for correcting the linearity of the sawtooth wave is provided between the vertical output circuit and the sawtooth wave generation circuit, and switching means connected in series to a parallel circuit of a resistor and a capacitor is provided. And a second feedback circuit for controlling a current supplied to a charging / discharging capacitor of the sawtooth wave generating circuit to keep a charging start position of the charging / discharging capacitor constant. A vertical deflection circuit, characterized in that connected to the feedback resistor and the charging and discharging capacitor.