JP3156425B2 - Horizontal AFC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a television receiver,
The present invention relates to a horizontal AFC circuit used for a video device such as a monitor device.

[0002]

2. Description of the Related Art A conventional horizontal AFC circuit will be described below. FIG. 8 is a circuit block diagram of a conventional horizontal AFC circuit. In FIG. 8, reference numeral 1 denotes a horizontal sync separation circuit for separating a horizontal sync signal from a composite video signal, and 2 detects a phase error between the horizontal sync signal and a flyback pulse (hereinafter, referred to as "FBP"). A phase comparator that outputs weighted bipolar current pulses, 3 is a filter that smoothes the output of the phase comparator 2, and 4 is a voltage-controlled oscillator (hereinafter, referred to as a voltage-controlled oscillator) that changes the oscillation frequency according to the DC output voltage of the filter 3. , VCO), 5 is a horizontal deflection output circuit that amplifies the output of the VCO, 6 is a high-voltage generation circuit that includes a deflection coil, a flyback coil, etc., and that generates a high-voltage FBP.
Is an integration circuit for integrating FBP.

[0003] The phase comparator 2 is a horizontal synchronizing signal to one input terminal (c) is input, it generates a current pulse I _s corresponding to the horizontal synchronizing signal (c) internally, and, to the other input terminal depending on the integrated waveform of FBP input (b) to isolate the current pulse I _s the positive pulse and a negative pulse, the polarity of different pulses in accordance with the phase difference of the horizontal synchronizing signal (c) FBP (a) and The weighting of the width is converted into a bipolar output current and output.

In such a conventional horizontal AFC circuit, a filter 3, a VCO 4, a horizontal deflection output circuit 5, a high voltage generation circuit 6, an integration circuit 7, and the other input of the phase comparator 2 are supplied from the output terminal of the phase comparator 2. An AFC feedback loop that returns in the order of the ends is formed.

Next, the operation of the conventional horizontal AFC circuit configured as described above will be described with reference to FIGS. FIGS. 9A to 9E show a conventional AFC.
FIG. 4 is a waveform chart for explaining the operation of the circuit. FIG. 9 (a)
Shows the waveform of the FBP output from the high voltage generation circuit 6,
The output signal of the VCO 4 is amplified by a horizontal deflection output circuit 5 and given to a high voltage generation circuit 6. As a result, a high voltage pulse generated by a deflection coil, a flyback coil or the like in the high voltage generation circuit 6 is limited to a predetermined level. This pulse is output at a predetermined peak value with reference to 0V. Then, FIG. 9 (b) by the integration circuit 7 indicates waveform obtained by integrating the FBP, which is integrated waveform which oscillates up and down relative to the reference potential V _s. FIG.
9C shows the voltage waveform of the horizontal synchronization signal output from the horizontal synchronization separation circuit 2. FIG.
3 shows a bipolar output current waveform of FIG. FIG. 9E shows FIG.
7B shows a bipolar output current waveform of the phase comparator 2 as in FIG. 7D, but a transient operation waveform of the output of the phase comparator 2 when the phase of the FBP advances.

[0006] The phase comparator 2 generates a current pulse I _s synchronized with the horizontal synchronizing signal (c) inputted from one input terminal once in the circuit. Then, the boundary of the intersection of the reference potential V _s indicated by the two-dot chain line in FIG. 9 (b), the output current and the negative polarity when the upper half-wave of the integrated waveform (the period from the intersection) through (b), below At the time of the side half-wave (the period from the intersection B to C), a bipolar current pulse with the output current being positive is output (see FIG. 9D).

[0007] The filter 3, a bipolar output current of the phase comparator 2 is smooth, and outputs a phase error voltage V _e corresponding to the DC current averaged. VCO4 connected to its output
Oscillates at a frequency corresponding to the level of the phase error voltage V _e of the output of the filter 3. FBP phase is horizontal sync signal (c)
If the flyback pulse is equal to FBP
When ₁ (indicated by the solid line in FIG. 9 (a)), its integrated waveform is as integrated waveform S ₁ shown by the solid line in FIG. 9 (b). At this time, the bipolar output current of the phase comparator 2 is as shown in FIG.
As shown in (d)), a positive pulse and a negative pulse having the same width and the same amplitude are output, and the phase error voltage V _e of the output of the filter 3 becomes zero.

[0008] Next, flyback pallets
Is FBP_Two (Shown by a broken line in FIG. 9A)
Is t₁ 9, the integrated waveform is correspondingly changed as shown in FIG.
(B) Integrated waveform S_Two Like t₁ The more advanced, the integrated waveform
From the initial point a to d, and the output of the phase comparison circuit 2
As shown in FIG. 9E, the pulse width on the negative polarity side of the pulse is
Transiently widens. And the filter 3
Output phase error voltage V_eBecomes negative potential. As a result,
The phase error voltage V of the output of the filter 3_e Depending on the VCO4
Oscillation frequency decreases, FBP_Two Phase is delayed. Soshi
As a result, the FBP coincides with the phase of the horizontal synchronizing signal.
Returning to the state shown by the solid line in FIG. _e Is again
Return to zero. Conversely, if the FBP phase is delayed,
The pulse width on the side transiently widens, and this time
Phase error voltage V of the output of filter 3_e Becomes a positive potential.
And the phase error voltage V_e Oscillation frequency of VCO4 according to
As the number increases, the phase of the FBP is advanced, and FIG.
When the state returns to the solid line, the phase error voltage V_e Becomes zero again
You. As described above, the horizontal AFC circuit is synchronized with the FBP and the horizontal AFC circuit.
VCO4 oscillates while matching the phase with the signal
You.

[0009]

However, in the above-mentioned conventional configuration, the period in which the high voltage generating circuit 6 generates the FBP corresponds to the horizontal blanking period of the video screen, and the return period depends on the setting error of the deflection coil of the video tube. Since the line period is not always displayed at an appropriate position on the screen, the phase difference between the FBP and the horizontal synchronizing signal is adjusted, and the retrace period (FBP) is set at an appropriate position on the screen. There must be. recent years,
These signal processing circuits have been increasingly integrated into ICs, and locations where external terminals are provided are considerably limited, and locations where large capacitances are connected are often used as external terminals.

The means for adjusting the phase of the FBP studied in the horizontal AFC circuit integrated into an IC will now be described. FIG.
Reference numeral 0 is a circuit diagram of the adjusting means when the conventional AFC circuit shown in FIG. 8 is integrated into an IC. In FIG. 10, the same portions as those in FIG. In FIG. 10, 8 to 13 are transistors, R1 to R5 are resistors, R
_v is a semi-fixed variable resistor, C ₁ and C ₂ are capacitances, V ₁ and V _s
Is a voltage source for bias, _Vcc is a power supply voltage terminal, 14 is a constant voltage diode, 15 is a frame representing an IC part,
16 is an external terminal of the IC, and 17 is an input terminal of a horizontal synchronizing signal.

The resistance R₁ And the constant voltage diode 14
The voltage level of the FBP output from the generation circuit 6 is adjusted to a predetermined level.
This is a circuit for limiting to a bell. The integrating circuit 7 has a resistor R_Two And content
Quantity C ₁ Composed of And the phase comparator 2
A collector circuit having active loads 12 and 13
A differential circuit 18 composed of transistors 10 and 11;
Of current pulse which generates current pulse and gives it to differential circuit 18
Means (transistors 8, 9 and resistor R_Five And voltage source V
₁ ).

Next, the circuit operation of FIG. 10 will be described with reference to FIG. FIGS. 11A to 11F show FIGS.
5 is an operation waveform diagram for explaining the operation of the conventional horizontal AFC circuit shown in FIG. FIG. 11A shows a waveform in which the FBP from the high voltage generation circuit 6 is restricted at a predetermined level.
FIG. 11B shows an integrated waveform obtained by integrating the FBP (FIG. 11A) by the integrating circuit 7, and FIG.
FIG. 11 shows a voltage waveform of a horizontal synchronizing signal inputted from FIG.
(D) shows a bipolar output current waveform of the phase comparator 2. Note Figure 11 (e) shows a bipolar output current waveform shown in FIG. 11 (d) in the same manner as the phase comparator 2, a phase comparator when the voltage drop V _r and the resistance value is increased in the resistance R _v is greater 3 shows a transient operation waveform of the output of the device 2. And FIG.
(F) shows the phase of the finally stabilized integrated waveform.

[0013] consists of a phase comparator 2 current pulse generating means (transistors 8 and 9, the resistor R ₅ and the voltage source V ₁₎ and the differential circuit 18, the current pulse generating means to produce a current pulse I _s input terminal transistor 8 is switching operation in response to the horizontal synchronizing signal input (see Figure 11 (c)) from 17, the bottom is zero, and peak value determined by the bias voltage and the resistor R ₅ of the voltage source V ₁ The current pulse _Is is generated in synchronization with the horizontal synchronizing signal.

On the other hand, the differential circuit 18 has active loads 12 and 13 in a collector circuit, and a resistor R ₃ ,
Through R ₄ predetermined bias voltage V _s (FIG. 11 (corresponding to V _s of b)) the differential pair transistors 1 are given
1 and 10 and the output of the current pulse generating means (transistor 9
Of collector) from the current pulse I _s it is given. Furthermore, the input signal obtained by integrating the FBP is input to the base of the transistor 10 via the capacitor C ₂ for binding. And
Differential circuit 18 switches the polarity of the current pulse I _s to the positive polarity and negative polarity and the upper half-wave and lower half waves of the integrated waveform, and outputs the bipolar output current to the filter 3.

A variable resistor R _v connected in series with the capacitor C ₁
Are used for phase adjustment, and when the variable resistor _Rv is zero, it operates similarly to the conventional AFC circuit shown in FIG. That is, when the variable resistor _Rv is zero in FIG.
FBP indicated by the solid line in (a) is inputted to the integration circuit 7, the output of the integrating circuit 7 becomes a state of S ₁ in FIG. 11 (b), the output of the differential circuit 18 is bipolar shown in FIG. 11 (d) Outputs the output current.

[0016] Next, the operation when the large resistance value of the variable resistor R _v. Increasing the resistance value of the variable resistor R _v, the voltage drop V _r of the variable resistor R _v is superimposed on the integrated waveform. Now, assuming that the voltage drop _Vr is superimposed on the integrated waveform, FIG.
1 assuming that a state of S ₂ indicated by a solid line in (b), the intersection between the integrated waveform reference potential V _s proceeds to ho from Lee, negative pulse bipolar output current of the output of the differential circuit 18 The width increases as shown in FIG. 11 (e), and the phase error voltage V _e
Becomes a negative voltage. As a result, the oscillation frequency of the VCO 4 becomes lower transiently, and the phase of the FBP is delayed. Then, the phase of the integrated waveform gradually delays, and the intersection E in FIG.
1 (f), the pulse width of the bipolar current pulse output from the differential circuit 18 is balanced between the positive and negative pulse widths, and the phase change of the FBP stops.

[0017] The foregoing description, for easy understanding of the description, but performed when a larger voltage drop V _r instantaneously, if adjusting the resistance value of the variable resistor R _v manually if to the extent that Deyutei bipolar output current changes slightly, remains substantially unchanged state and bipolar output current waveform of FIG. 11 (d), the according to the change of the variable resistor R _v FB
The phase of P can be adjusted smoothly.

In any case, the above-mentioned means has a problem that the phase of the FBP can be adjusted only in one direction with respect to the horizontal synchronizing signal, and furthermore, in the direction lagging behind.

An object of the present invention is to provide a horizontal AFC circuit in which the phase of a flyback pulse (FBP) can be adjusted back and forth with respect to a horizontal synchronization signal.

[0020]

In order to achieve the above object, a first horizontal AFC circuit according to the present invention is provided for converting a composite video signal.
A signal corresponding to the separated horizontal synchronization signal and high-voltage pulse signal
Are individually input to the input terminal pair, and according to the phase difference between the two signals.
A phase comparator that outputs the output phase error signal to an output terminal;
A smoothed signal obtained by smoothing the phase error signal input to the input terminal.
Signal to the output terminal and a filter to the input terminal.
Oscillation signal having a different frequency value according to the value of the smoothed signal
Voltage-controlled oscillator that outputs a signal to the output terminal, and an input terminal
The amplified signal of the oscillation signal input to
Horizontal deflection output circuit to output and before input to input terminal
The high-voltage pulse signal is output based on the output signal of the horizontal deflection output circuit.
Signal to the output terminal and input to the input terminal.
An output terminal for outputting a signal obtained by integrating the input high-voltage pulse signal
And an integrating circuit for outputting to the phase comparator,
Filter, voltage controlled oscillator, horizontal deflection output circuit, high voltage generation
Forming a feedback loop by the circuit and the integrating circuit,
Horizontal AFC for synchronizing a high voltage pulse with the horizontal synchronization signal
Circuit, wherein the phase comparator is connected to a base terminal pair.
1. When a predetermined potential is individually applied through the second resistor
Both differential pair transistors that take out the signal from the collector
And a current pulse synchronized with the horizontal synchronization signal
Generation of a current pulse applied to the emitter junction of a pair transistor
Generating means, and one of the first resistor and the base terminal pair.
And a current source for supplying a current to the connection portion of
The switching operation is performed in synchronization with the high-voltage pulse .

[0021]

Next, the second horizontal AFC circuit of the present invention
In addition to the configuration of the first horizontal AFC circuit of the present invention, a current source that supplies a current to one end of the first resistor has a configuration that performs a switching operation in synchronization with FBP .
It has a transistor pair that constitutes a differential circuit.
A DC current is applied to the emitter-coupled part of the
When the high-voltage pulse is applied to one base of a transistor pair,
Together, apply a reference voltage to the other base and
You output a signal corresponding to the high voltage pulse.

[0023]

According to the above arrangement, in the first invention,
The current source performs a switching operation synchronized with the FBP.
Therefore, the potential of the reference input is level-shifted in synchronization with FBP
However, even in the range exceeding the FBP pulse width, the FBP phase
Adjustment is possible, and the FBP phase can be adjusted over a wide range.
You.

[0024]

Further, in the second invention, the current source is a differential current source.
And a pair of transistors constituting a driving circuit.
DC current is applied to the emitter-coupled part of the
When the high-voltage pulse is applied to one base of the
And apply a reference voltage to the other base
Since a signal corresponding to the pressure pulse is output , the potential of the reference input is level-shifted in synchronization with the FBP, and the phase of the FBP can be adjusted even in a range exceeding the pulse width of the FBP.
The BP phase can be adjusted over a wide range.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a horizontal AFC circuit according to an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram of a horizontal AFC circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 2 denotes a phase comparator which detects a phase error between the horizontal synchronizing signal and the FBP, and outputs a bipolar output current weighted to a positive polarity and a negative polarity, and 3 smoothes the output current of the phase comparator 2. Filter 4, a VCO that varies the oscillation frequency according to the DC output voltage of the filter 3, 5 a horizontal deflection output circuit that amplifies the output of the VCO 4, 6 a deflection coil, a flyback coil, and the like. A high-voltage generating circuit for generating FBP; 7 an integrating circuit for integrating FBP;
Is a transistor, 14 is a constant voltage diode, 17 is an input terminal of a horizontal synchronization signal, 18 is a differential circuit, 19 to 22 are transistors, 23 is a current source, V ₁ , V ₂ and V _s are bias voltage sources. V _cc is the power supply voltage terminal, R ₁ to R ₇ are resistors, C _1, C ₂ is the capacitance. The current pulse generating means includes:
And transistors 8 and 9, and the resistor R _5, made from the voltage source V ₁ Prefecture, as the emitter potential of the transistor 9 is substantially fixed potential, based on the bias voltage of the voltage source V ₁ of the transistor 9 is applied, the input The switching operation of the transistor 8 is performed by the horizontal synchronization signal supplied from the terminal 17. Then, the peak value of the current is determined by the resistor R _5, and generates a current pulse I _s synchronized with the horizontal synchronizing signal, the current pulse I _s is the differential pair transistors 10, 1
One emitter coupling point.

The bidirectional current source has active loads 21 and 22 in the collector circuit, and the current source 2 is connected to the emitter junction.
3 is connected to the differential pair transistors 19 and 20. The base of the transistor 19 is biased by the voltage source V _s and the voltage source V is connected to the base of the transistor 20.
Controlled by ₂ . The polarity and absolute value of the output current depend on the voltage source V
It is controlled by a _second control voltage, providing an output current from the output end of Akuteibu load (collector of transistor 22) to one end of the first resistor R _3. Note that the differential pair transistor 1
Resistors R ₆ and R ₇ provided in the emitter circuits 9 and 20
, When the resistance value is increased, the gradient of the variation of the output current to the variation control voltage V ₂ is reduced, it is also fine adjustment of the output current of the bidirectional current source. In the present embodiment, a circuit based on the differential circuit 18 is used. However, a bidirectional current source can be configured by combining positive and negative current sources, and fixing one of them and changing the other. , Can be configured as a bidirectional current source even if both are simultaneously variable.

The phase comparator 2 has active loads 12 and 13 in a collector circuit, and a resistor R in both bases.
_3, through the R ₄ consists of the differential pair transistors 11 and 10 given the predetermined bias voltage V _s differential circuit 1
8, and a current pulse generating means comprises from a bidirectional current source (a transistor 19 to 22), the output signal of the integrator circuit 7 is input to the base of the transistor 10 via the capacitor C ₂ for binding. The differential circuit 18 switches the polarity of the current pulse I _s in the upper half-wave and lower half waves of the integrated waveform in the positive polarity and negative polarity, the filter 3 a bipolar output current
Output to

The horizontal AFC circuit according to the first embodiment includes an output terminal of the phase comparator 2, a filter 3, a VCO 4,
A path is drawn in the order of the horizontal deflection output circuit 5, the high voltage generation circuit 6, the integration circuit 7, and the input terminal of the phase comparator 2 to form an AFC feedback loop.

Next, the operation of the horizontal AFC circuit thus configured will be described with reference to the operation waveform diagram of FIG. FIGS. 2A to 2F are operation waveform diagrams for explaining the operation of the horizontal AFC circuit according to the first embodiment of the present invention. FIG. 2A shows an FBP waveform in which a high-voltage pulse output from the high-voltage generating circuit 6 is limited to a predetermined level by a limiting circuit including a resistor R ₁ and a constant voltage diode 14. The solid line indicates a state when the phases of FBP ₁ and the horizontal synchronization signal match. The broken line indicates the resistance R ₃
To give a current, results of voltage drop V _x was generated across the resistance R _3, showing a state where the advanced relative to the phase a horizontal synchronization signal of FBP _2.

FIG. 2B shows the FBP ₁ by the integrating circuit 7.
FIG. 2 shows a waveform S ₁ obtained by integrating (shown in FIG. 2A)
(C) shows the voltage waveform of the horizontal synchronization signal output from the horizontal synchronization separation circuit 2. The current pulse of the current pulse generating means is also generated in synchronization with the horizontal synchronizing signal. FIG.
(D) shows the waveform of the bipolar output current of the phase comparator 2 when the horizontal synchronization signal and the FBP are synchronized. FIG. 2 (e)
FIG. 2D shows the waveform of the bipolar output current of the phase comparator 2 as in FIG. 2D, but shows the transient operation waveform of the output of the phase comparator 2 when the phase of the FBP advances. FIG. 2 (f) shows the phase of the finally stabilized integrated waveform.

The current generating means (transistor) in the phase comparator 2
Stars 8, 9 and resistor R_Five ) Is input from the input terminal 17
In response to the horizontal synchronization signal (shown in FIG.
Flow pulse I_s Generate A bidirectional current source (transformer)
If the output current of each of the transistors 19 to 22 is zero,
The bases of the differential pair transistors 10 and 11 have a reference potential V _s 
Biased to the same potential as And the coupling capacity C
_Two The integrated waveform (shown in FIG. 2 (a)) is
When input to the base of the _s Is the base
With reference to the quasi-input potential (base potential of transistor 11)
The upper half wave and lower half wave of the integrated waveform input.
The continuity between the transistors 10 and 11 is alternately switched, and the phase ratio
Output terminal of comparator 2 (collector of transistor 10)
It outputs as a characteristic output current. That is, FIG.
Reference potential V indicated by a chain line_s At the intersection with
S_s Switch the polarity of the upper half wave (intersection
Output current is negative during the period from to
Output current is positive during half-wave (period from intersection B to C)
(See FIG. 2 (d).)
See).

Next, the filter 3, a bipolar output current of the phase comparator 2 is smooth, and outputs a phase error voltage V _e corresponding to the phase difference between the FBP and the horizontal synchronizing signal. This phase error voltage V _e becomes zero if there is no phase difference between the FBP and the horizontal synchronizing signal (when the pulse widths of the positive polarity pulse and the negative polarity pulse of the bipolar output current are equal). On the other hand, when the phase of the FBP advances, a negative error voltage is output, and when the phase is delayed, a positive error voltage is output.

[0035] Then, VCO 4 oscillates at a frequency corresponding to the level of the phase error voltage V _e of the output of the filter 3. F
BP is synchronized with the oscillation output of VCO4,
When the phase with the horizontal synchronizing signal coincides, the flyback pulse is as shown by a solid line FBP ₁ in FIG. 2A, and its integrated waveform is as shown by a solid line S _{1 in} FIG. 2B. At this time, as shown in FIG. 2 (d), the bipolar output current of the phase comparator 2 is such that a positive pulse and a negative pulse having the same width are output in a vertically symmetrical manner, and the output of the filter 3 averages them to obtain a DC output. and outputs a phase error voltage V _e, the phase error voltage V _e at this time is zero. Then, for example, when the phase of FBP advances, the AFC loop outputs a negative phase error voltage V
_e is output to lower the oscillation frequency of the VCO 4 to delay the phase of the FBP. Conversely, if the phase is delayed, the oscillation frequency of the VCO 4 is increased to advance the phase. Thus, the horizontal AFC circuit controls the oscillation frequency of the VCO 4 so that the phase of the FBP matches the horizontal synchronization signal.

Next, the phase adjustment of the FBP will be described. For example, to advance the phase of FBP, the voltage source V ₂
Is set higher than the reference voltage source V _s, and a current flows from the transistor 22 to the resistor R ₃ , causing a positive voltage drop across the resistor R ₃ . When the voltage drop and V _3, the comparison input of the potential of the differential circuit 18 (base potential of the transistor 11) rises to (V _s + V _3). Then, the switching point of the bipolar output current switched by the phase comparison circuit 2 is the intersection A when the output current of the bidirectional current source is zero.
What has been (b) and (c) moves to intersections (h), (h), and (h) as the potential of the reference input rises. When this potential instantaneously moves, the waveform of the bipolar output current has a narrower current pulse width on the negative polarity side as shown in FIG. 2E, and the positive phase error voltage V Outputs _e . Then, the oscillation frequency of the VCO 4 increases according to the positive phase error voltage V _e , the phase is advanced from FBP ₁ to FBP ₂ , and the positive and negative pulses of the bipolar output current are balanced. The intersection of the potential of the reference input and the integrated waveform advances to the level shown in FIG. 2 (f), and the positive polarity pulse and the negative polarity pulse of the bipolar output current are shown in FIG.
The transition of the phase is stopped by balancing as shown in (d). The foregoing description, for easy understanding of the operation has been described the operation when the potential of the reference input instantaneously raised, the operation setting of the variable voltage source V ₂ manually, the reference input slowly Following the potential change, the phase of the FBP can be adjusted in a state where the duty of the bipolar output current hardly collapses.

On the other hand, when the phase of the FBP is delayed, the voltage source V ₂ is set lower than the reference voltage source V _s, current is drawn from the resistor R ₃ from the transistor 22, and a negative voltage drop is applied across the resistor R _3. It may be caused. Then, the oscillation frequency of the VCO 4 decreases according to the negative phase error voltage V _e ,
The phase of the FBP moves in the direction of delay, and the transition of the phase is completed in a state where the positive-polarity pulse and the negative-polarity pulse of the bipolar output current are balanced (shown in FIG. 2D).

As described above, the horizontal AF of this embodiment
In the C circuit, the phase comparator 2 is adjusted by adjusting the bidirectional current source.
The potential of the reference input is adjusted up and down, the switching operation point (cross point of the reference input and the integral waveform) between the positive polarity pulse and the negative polarity pulse of the bipolar output current is changed, and the phase of the FBP is changed to the horizontal synchronization signal. Can be adjusted before and after.

Second Embodiment Hereinafter, a horizontal AFC circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram of a horizontal AFC circuit according to a second embodiment of the present invention. In FIG. 3, reference numeral 2 denotes a phase comparator which detects a phase error between the horizontal synchronizing signal and the FBP, and outputs a bipolar output current weighted to a positive polarity and a negative polarity, and 3 smoothes the output current of the phase comparator 2. Filter,
Reference numeral 4 denotes a VCO that varies the oscillation frequency in accordance with the DC output voltage of the filter 3, 5 denotes a horizontal deflection output circuit that amplifies the VCO output, and 6 denotes a high voltage that includes a deflection coil and a flyback coil and generates a high-voltage FBP. Generating circuit, 7 is FBP
An integration circuit for integrating, 8 to 13 are transistors, 14 is a constant voltage diode, 17 is an input terminal for a horizontal synchronization signal,
24 is a current source, V ₁ and V _s are voltage sources for bias, V _cc
Is a power supply voltage terminal, R _{1 to} R ₅ and R ₈ are resistors, C ₁ and C ₂
Is the capacity.

The current pulse generating means includes a transistor 8,
9, and the resistor R _5, made from the voltage source V ₁ Prefecture, as the emitter potential of the transistor 9 is substantially fixed potential, based on the bias voltage of the voltage source V ₁ of the transistor 9 is applied, the external terminal 17 The switching operation of the transistor 8 is performed by the applied horizontal synchronization signal. Then, the peak value of the current is determined by the resistor R _5, and generates a current pulse I _s synchronized with the horizontal synchronizing signal, the current pulse I _s is supplied to the emitter point of attachment of the differential pair transistors 10, 11.

Next, the phase comparator 2 has active loads 12 and 13 in a collector circuit, and a resistor R ₃ ,
Through R ₄ consists of the differential pair transistors 11 and 10 given the predetermined bias voltage V _s differential circuit 18
When a current pulse generating means, the output signal of the integrator circuit 7 is input to the base of the transistor 10 via the capacitor C ₂ for binding. Then, the differential circuit 18 switches the current pulse between positive polarity and negative polarity with the upper half wave and the lower half wave of the integrated waveform, and outputs the bipolar output current to the filter 3. However,
Reference input of phase comparator 2 (base of transistor 11)
Is different from the first embodiment in that the bias voltage can be varied by supplying the current from the current source 24.

The integrating circuit 7 includes a resistor R in series with the capacitor C _1.
8 is different from the first embodiment in that the capacitor C ₁ is added.
Inter-terminal voltage of the series circuit of a resistor R ₈ is in the configuration given to the comparison input of the phase comparator 2 (the base of the transistor 10) and.

The horizontal AFC circuit according to the second invention comprises an output terminal of the phase comparator 2, a filter 3, a VCO 4,
A path is drawn in the order of the horizontal deflection output circuit 5, the high voltage generation circuit 6, the integration circuit 7, and the input terminal of the phase comparator 2 to form an AFC feedback loop as in the first embodiment.

Next, the horizontal AFC circuit constructed as described above is used.
The operation of the road will be described with reference to the operation waveform diagram of FIG.
I will tell. 4 (a) to 4 (f) show the horizontal AFC cycle shown in FIG.
It is an operation | movement waveform diagram for demonstrating operation | movement of a road. FIG.
(A) shows a high-voltage pulse output from the high-voltage generation circuit 6.
Resistance R ₁ And a limiting circuit composed of a constant voltage diode 14
5 shows an FBP waveform limited to a predetermined level. Real
The wire has the appropriate resistance R₈ Is the capacity C₁ Insert in series with FBP
₁ Indicates that the phase of the
You. The broken line indicates the resistance R_Three The current from the current source 24
Give resistance R_Three Voltage drop between terminals_x That resulted in
Fruit FBP_Two State that the phase of the
Show.

FIG. 4B shows that the integration circuit 7 controls the FBP.
₁ (See FIG. 4 (a)) integrated waveform S₁ Is shown. No.
The integrating circuit (indicated by 7 in FIG. 1) used in the first embodiment is a resistor
R_TwoAnd capacity C₁ Which simply integrates the FBP waveform
Triangular wave with capacitance C₁ Output between the terminals
(See FIG. 2B), the integration circuit used in the second embodiment
7 is the capacity C₁ Resistor R in series with₈ Are connected and their series times
The voltage between the terminals of the path is input to the phase comparator 2. for that reason
The input signal of the phase comparator 2 is the peak value V of the FBP. _p The
Anti-R_Two And resistance R₈ And the resistance R when divided by₈ Between terminals
Voltage (square wave) and capacitance C₁ And resistance (R_Two + R₈ ) And time
It becomes a waveform obtained by adding a triangular wave integrated by a constant.

FIG. 4C shows an output from the horizontal sync separation circuit 2.
Indicates the voltage waveform of the horizontal synchronization signal
Current pulse I generated by raw means_s Also this horizontal sync signal
Generated in sync with When the current of the current source 24 is zero,
If present, bases of differential pair transistors 10 and 11 are reference
Potential V_s And the coupling capacitance C _Two 
The integrated waveform (see FIG. 4A) is output through the transistor
10, the current pulse I_s Is the standard
With reference to the input potential (base potential of transistor 11)
The upper half wave and lower half wave of the integrated waveform input.
The phase comparator 2 alternately switches the conduction between the
Output terminal (collector of transistor 10)
Output as current. That is, the two-dot chain line in FIG.
Reference potential V indicated by_s The current pulse I at the intersection with_s 
Switch the polarity of the upper half-wave of the integrated waveform (
The output current is negative and the lower half-wave
The output current is positive when the
(FIG. 4B)
(D)).

FIG. 4D shows the waveform of the bipolar output current of the phase comparator 2 when the horizontal synchronizing signal and the FBP are synchronized in phase. Further, FIG.
The waveform of the bipolar output current of the phase comparator 2 is shown similarly to (d), but is a transient operation waveform of the bipolar output current of the phase comparator 2 in the process of advancing the phase of the FBP. FIG. 4 (f)
Indicates the phase of the finally stabilized integrated waveform.

The method of adjusting the phase of the horizontal AFC circuit in the second embodiment is as follows. First, with the current value of the current source 24 set to zero, the maximum delay phase within a desired variable range with respect to the horizontal synchronizing signal is determined by the FBP. preset the resistance value of the resistor R ₈ to be to. The voltage drop V _r of the resistor R ₈ is increased, the rising of the integrated waveform is faster depending on its size, delay the phase of FBP for similar horizontal synchronizing signal and the operation waveforms of the conventional horizontal AFC circuit shown in FIG. 11 Can be synchronized. The solid line FBP ₁ in FIG.
The operation waveforms of (b), (c), and (d) show a state in which the phase of the FBP is delayed and synchronized. At this time, assuming that the pulse width of the horizontal synchronizing signal is t as shown in FIG. 4C, the bipolar output current is such that the pulse width of the positive polarity pulse is t / 2 and the negative polarity is negative as shown in FIG. It is stabilized when the pulse width of the pulse is t / 2.

Next, poured current from the current source 24 to the resistor R _3, raising the potential of the reference input (base of transistor 11). Then, in response to an increase in the first similarly reference input to that described in Example potential above (V _s + V _3), the switching operation point of the bipolar output current of the phase comparator 2 (reference input and an integral waveform 4) is set to the rear of the FBP ₁ (cross point Y in FIG. 4B), and the positive polarity side of the bipolar output current of the phase comparator 2 is transiently wide as shown in FIG. And the phase of the FBP is advanced. Then, when the phase of the integrated waveform advances and the intersection Y in FIG. 4B reaches a position corresponding to the center point of the horizontal synchronization signal, that is, the position of the intersection S in FIG. FIG. 4 (d)
Then, the relative position between the FBP and the horizontal synchronizing signal is fixed, and the FBP and the horizontal synchronizing signal oscillate synchronously. That is, the resistance R ₈ functions in the direction of delaying the phase of FBP, the voltage drop V _r of the resistor R ₃ functions in the direction of advancing the phase of FBP, the phase of FBP and as a result can be adjusted before and after the horizontal sync signal.

[0050] Note that in the second embodiment, to increase the resistance of the resistor R _8, it is possible to delay the FBP phase The larger setting the voltage drop V _r, the slope of the triangular wave component is small is it to extremely large resistance R ₈ for chattering to an output current of the phase comparator 2 is liable to occur when noise is mixed is not preferable. 1/4 of the magnitude of the voltage drop V _r developed across resistor R ₈ is the amplitude of the integrated waveform
It is preferable to set the degree to the maximum value.

[0051] In the second embodiment, delay the advance phase by setting the resistor R _8, and adjusted to the direction of advancing the phase by changing the current value of the current source 24, before and after the phase of FBP of the horizontal synchronizing signal as a result the showed what can be adjusted, advance the advance phase settings of the current source 24 in the reverse, the same effect can be adjusted in the direction of delaying the phase by changing the resistor R ₈ is of course obtained.

As described above, in the second embodiment, F
The BP phase can be adjusted before and after the horizontal synchronization signal.
When the potential (V _s + V ₃ ) of the reference input increases and the period T ₁ of the upper half wave of the integrated waveform becomes smaller than t / 2, the horizontal A
FC loop phase adjustment fails. That is, F
Even though the phase of the BP can be adjusted back and forth, the adjustment is such that the center of the FBP can be slightly varied with respect to the center of the horizontal synchronization signal within a range where the horizontal synchronization signal is completely included within the pulse width of the FBP. Range. Solve this point,
The third embodiment described below further expands the FBP adjustment range.

(Third Embodiment) Hereinafter, a horizontal AFC circuit according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a circuit diagram of a horizontal AFC circuit according to a third embodiment of the present invention. In FIG. 5, the same parts as those in the second embodiment shown in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. Only different points from the second embodiment will be described. In FIG. 5, 8 to 13 and 25 to 29 are transistors, R _{2 to} R ₅ , R ₈ and R ₉ are resistors, 30 is a variable current source, 31 is a current source, and 32 is a bias voltage source.

As shown in FIG. 5, the transistors 27 and 28 constituting the differential circuit compare the FBP signal based on the bias voltage source 32 to switch the output current of the variable current source 30 to perform the switching operation. Variable current source 30 mirror-inverted through a current mirror constituted by 26
Of the output current of the phase comparator 2 (transistor 1
1 base). Note the voltage value of the bias voltage source 32 is preferably about 1/2 of the level of the peak value V _p of FBP.

As described above, the third embodiment is different from the second embodiment in that the current source 24 in the second embodiment is switched by synchronizing the potential of the reference input with the FBP. .

Next, the operation of the horizontal AFC circuit thus configured will be described with reference to the operation waveform diagram of FIG. FIG 6 (a) ~ (f) is an operation waveform diagram for explaining the operation of the horizontal AFC circuit shown in FIG. 5, the resistor R ₃
The voltage drop V ₃ of shows operation waveforms when extremely large.

FIG. 6A shows a waveform of the FBP in which the high-voltage pulse output from the high-voltage generating circuit 6 is limited to a predetermined level by a limiting circuit composed of the resistor R ₁ and the constant voltage diode 14, and FIG. ) Is FBP by the integration circuit 7.
FIG. 6 shows a waveform S obtained by integrating (see FIG. 6A).
6C shows a voltage waveform of the horizontal synchronizing signal input from the input terminal 17, and FIG. 6D shows a waveform of the bipolar output current of the phase comparator 2. Note the current pulse I _s generated by a current pulse generating means is also generated in synchronization with the horizontal synchronizing signal.

In the horizontal AFC according to the third embodiment, the transistors 27 and 28 forming a differential circuit compare the FBP with the bias voltage source 32 to perform a switching operation on the output current of the variable current source 30, and Is input to the reference input (base of the transistor 11) of the phase comparator 2 only when the input is input. Then the voltage drop V ₃ of the resistor R ₃ is generated synchronously with FBP, the phase comparator 2
The potential of the reference input is switched to the two potentials of the reference potential V _s and (V _s + V ₃₎ as the two-dot chain line in FIG. 6 (b). When the integral waveform S is input to the base of the transistor 10, the current pulse I _s is the reference input voltage (Fig. 6
Based on the two-dot chain line of (b), the conduction of the transistors 10 and 11 is alternately switched between the upper half wave and the lower half wave of the integrated waveform input, and the output terminal of the phase comparator 2 (transistor 10
Output the bipolar output current. That is,
When the potential of the integrated waveform becomes high at the intersection (T, N, N, R, M) of the reference input potential indicated by the two-dot chain line in FIG. And the output current is set to negative polarity during the period from the intersection point to the point la), and the output current is set to the positive polarity when the integrated waveform becomes low potential (the period from the intersection point to the point m). The phase comparator 2 outputs.

The method of adjusting the phase of the horizontal AFC circuit in the third embodiment is basically the same as that in the second embodiment. In a third embodiment, the spike noise n occurs (V _s + V ₃₎ of the raising to the vicinity peak value of the integrated waveform bipolar output current. This phenomenon occurs because both the differential pair transistors 10 and 11 conduct because the reference input and the integrated waveform match between (intersection point n and intersection point n).
This phenomenon is by no means favorable, but (V _s +
The range in which the potential of V ₃ ) reaches the peak value of the integrated waveform is such that the intersection changes along the rising slope of the integrated waveform, and the operation from the intersection n to the intersection la does not drop the negative polarity pulse. Therefore, there is no problem at all. The ultimate state of the operation of the third embodiment is the peak value of the integrated waveform and (V _s + V
₃ ) coincides with each other, and it does not matter if the horizontal synchronizing signal protrudes into the range from the intersection point n to the intersection point la by the amount of the negative polarity pulse. Therefore, as shown in FIG. Is t, the FBP is t / t compared to the second embodiment.
Adjustment to advance by 2 is possible.

For reference, when the potential of the reference input is raised to the position (V _s + V ₃ ) shown in FIG. 6 in the circuit configuration of the second embodiment shown in FIG. Since the potential becomes lower than the potential of the reference input, the bipolar output current becomes as shown in FIG. Therefore, the FB that the positive pulse and the negative pulse should originally be equal
Even phase relationship between P and the horizontal synchronizing signal, it would be further advance the phase of FBP from the components of the positive pulse becomes larger, in the case of the second embodiment shown in FIG. 6 (V _s
Synchronization and adjustment of the phase of the FBP cannot be performed up to a high potential such as + V ₃ ).

(Fourth Embodiment) A horizontal AFC circuit according to a fourth embodiment of the present invention will be described below with reference to FIG. FIG. 7 is a circuit diagram of a horizontal AFC circuit according to a fourth embodiment of the present invention. In FIG. 7, the same portions as those of the third embodiment shown in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted. Only different points from the third embodiment will be described. In FIG. 7, 8 to 13, 33 and 34 are transistors, R _{2 to} R ₅ , R ₈ and R ₉ are resistors, 31 is a current source, 3
2 is a bias voltage source.

Transistors 33 and 3 constituting a differential circuit
4 is F based on the bias voltage of the bias voltage source 32.
The BP is compared to switch the current source 31 that supplies a current to the common emitter connection point of the transistors 33 and 34,
The difference from the third embodiment shown in FIG. 5 is that the collector current of the transistor 34 is directly applied to the reference input (base of the transistor 11) of the phase comparator 2. In the embodiments other than the third embodiment, it is a little difficult that the sensitivity converted into the FBP input voltage for switching the current supplied to the reference input terminal is deteriorated as compared with the third embodiment. If the input signal level is equal to or higher than volts, there is no problem. In particular, the FBP limited by the constant voltage diode 14 as in this embodiment has no problem because it has a sufficient amplitude.

The fourth embodiment shown in FIG. 7 is suitable for integration in a semiconductor integrated circuit since the number of elements constituting the circuit is small, and the FB is set in advance by setting the current value of the current source 31.
Complete the P phase, if so adjusted by varying the resistance R _8, which are external to the direction of delaying the phase of FBP, the semiconductor integrated circuit in which the external terminals to a minimum can be realized.

The voltage value of the bias voltage source 32 is FB
Preferably to about 1/2 of the level of the peak value V _p of P. In the fourth embodiment, previously delayed phase by setting the resistor R _8, and adjusted to the direction of advancing the phase by changing the current value of the current source 31, the phase of the FBP resulting can be adjusted before and after the horizontal synchronizing signal showed things, promote advance phase settings of the current source 31 in the reverse, the same effect can be adjusted in the direction of delaying the phase by changing the resistor R ₈ is of course obtained.

[0065]

As described above, the first horizontal A according to the present invention is provided.
In the FC circuit, the current source is switched in synchronization with FBP
In order to perform the operation, the potential of the reference input is synchronized with FBP.
Bell shift, FB even in the range exceeding the pulse width of FBP
Adjustment of the phase of P becomes possible, and adjustment of the phase of FBP becomes wider.
Range.

[0066]

Further, in the second horizontal AFC circuit according to the present invention, the current source includes a transistor pair forming a differential circuit.
A DC current is applied to the emitter coupling part of this transistor pair.
And the base of one of the transistors
And a reference voltage to the other base.
In order to output a signal corresponding to the high-voltage pulse from the collector , the potential of the reference input is level-shifted in synchronization with the FBP, and the phase of the FBP can be adjusted even in a range exceeding the pulse width of the FBP. , FBP can be adjusted over a wide range.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a horizontal AFC circuit according to a first embodiment of the present invention.

FIGS. 2A to 2F are operation waveform diagrams for explaining the operation of the horizontal AFC circuit according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram of a horizontal AFC circuit according to a second embodiment of the present invention.

FIGS. 4A to 4F are operation waveform diagrams for explaining the operation of the horizontal AFC circuit according to the second embodiment of the present invention;

FIG. 5 is a circuit diagram of a horizontal AFC circuit according to a third embodiment of the present invention.

FIGS. 6A to 6F are operation waveform diagrams for explaining the operation of the horizontal AFC circuit according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram of a horizontal AFC circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit block diagram of a conventional horizontal AFC circuit.

9 (a) to 9 (e) are operation waveform diagrams for explaining the operation of a conventional AFC circuit.

FIG. 10 is a circuit diagram of adjusting means when a conventional AFC circuit is integrated into an IC.

FIGS. 11A to 11F are horizontal AFs of a conventional IC.
Operation waveform diagram for explaining operation of C circuit

[Explanation of symbols]

2 phase comparator 3 filter 4 VCO 5 horizontal deflection output circuit 6 high-voltage generation circuit 7 integrating circuits 10 and 11 the differential pair transistors 12 and 13 Akuteibu load 14 constant-voltage diode R ₃ first resistor R ₄ second resistor

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-51-60149 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (2)

(57) [Claims] 1. A horizontal synchronizing signal separated from a composite video signal.
Signal and the signal corresponding to the high-voltage pulse signal
And outputs a phase error signal corresponding to the phase difference between the two signals.
The phase comparator that outputs to the terminal and the one before input to the input terminal
The smoothed signal obtained by smoothing the phase error signal is output to the output terminal.
Filter and the value of the smoothed signal input to the input terminal
Output an oscillation signal with a different frequency value to the output terminal.
Voltage controlled oscillator, and the oscillation input to an input terminal.
Horizontal deflection output that outputs the amplified signal to the output terminal
Circuit, and the horizontal deflection output circuit input to the input terminal.
Outputting the high-voltage pulse signal to an output terminal based on the output signal;
High-voltage generating circuit, and the high-voltage pulse input to an input terminal.
An integration circuit that outputs a signal obtained by integrating the input signal to an output terminal;
The phase comparison circuit, a filter, and a voltage-controlled oscillation
, Horizontal deflection output circuit, high voltage generation circuit and integration circuit
Therefore, a feedback loop is formed so that the high-voltage pulse
A horizontal AFC circuit for synchronizing with a synchronization signal, wherein the phase comparator is configured such that a predetermined potential is individually applied to a pair of base terminals via first and second resistors, and a predetermined potential is applied from a collector.
A differential pair transistors extracting a signal, the horizontal synchronization signal
Current pulse synchronized with the differential pair transistor.
A current pulse generating means for applying the current pulse to the
And a current source for applying a current to a connection between the resistor and one of the base terminal pairs, and the current source performs a switching operation in synchronization with the high-voltage pulse.
A horizontal AFC circuit characterized by making. 2. The method according to claim 1, wherein the current source is a transformer forming a differential circuit.
Transistor pair and the emitter coupling of this transistor pair
Section of the transistor pair.
To the other base
A signal corresponding to the high voltage pulse from the collector by applying a voltage
2. A horizontal AFC according to claim 1, wherein
circuit.