JPH06253171A - Horizontal afc circuit - Google Patents

Abstract

PURPOSE:To adjust the phase of a flyback pulse (FBB) in forward/backward directions with respect to a horizontal synchronizing signal by varying vertically the potential of a reference input with a current supplied from a current source. CONSTITUTION:A phase comparator 2 has active loads 12, 13 in a collector circuit, differential pair transistors(TRs) 10, 11 whose both bases receive a predetermined potential via 1st and 2nd resistors R3, R4, current pulse generating means 8, 9 comprising a resistor R5 and a capacitor V1 and giving a current pulse synchronously with a horizontal synchronizing signal to an emitter coupling node of the differential pair TRs 10, 11 and 2-way current sources 19-22 connecting to one terminal of the 1st resistor R3 and generating a current adjusted to positive and negative polarities. An output signal of an integration circuit 7 is inputted to one base input to which a 2nd resistor R4 is connected. Then the potential of the reference input is vertically varied by the 2-way current and the cross point between the integration waveform and the potential of the reference input is moved in response to the vertical movement of the reference potential Vs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a television receiver,
The present invention relates to a horizontal AFC circuit used for video equipment such as a monitor device.

[0002]

2. Description of the Related Art A conventional horizontal AFC circuit will be described below. FIG. 8 is a circuit block diagram of a conventional horizontal AFC circuit. In FIG. 8, 1 is a horizontal sync separation circuit that separates a horizontal sync signal from a composite video signal, and 2 is a phase error between the horizontal sync signal and a flyback pulse (hereinafter, referred to as FBP), and the positive and negative polarities are detected. A phase comparator that outputs a weighted bipolar current pulse, 3 is a filter that smoothes the output of the phase comparator 2, and 4 is a voltage-controlled oscillator that changes the oscillation frequency according to the DC output voltage of the filter 3 , VCO) 5 is a horizontal deflection output circuit that amplifies the VCO output, 6 is a high voltage generation circuit that includes a deflection coil and a flyback coil, and that generates a high voltage FBP, 7
Is an integrating circuit for integrating the FBP.

The phase comparator 2 receives the horizontal synchronizing signal (c) at one input end thereof, internally generates a current pulse I _s according to the horizontal synchronizing signal (c), and then at the other input end thereof. The current pulse I _s is divided into a positive polarity pulse and a negative polarity pulse according to the integrated waveform (b) of the input FBP, and a pulse having a different polarity depending on the phase difference between the horizontal synchronization signal (c) and FBP (a). The weighting of the width is converted into a bipolar output current that changes and is output.

In such a conventional horizontal AFC circuit, the filter 3, the VCO 4, the horizontal deflection output circuit 5, the high voltage generating circuit 6, the integrating circuit 7, and the other input of the phase comparator 2 are output from the output terminal of the phase comparator 2. It forms an AFC feedback loop that returns in the order of ends.

Next, the operation of the conventional horizontal AFC circuit configured as described above will be described with reference to FIGS. 9 (a) to 9 (e). 9A to 9E are conventional AFCs.
It is a waveform diagram for explaining the operation of the circuit. FIG. 9 (a)
Shows the waveform of the FBP output from the high voltage generation circuit 6,
The output signal of the VCO 4 is amplified by the horizontal deflection output circuit 5 and applied to the high voltage generation circuit 6, and as a result, a high voltage pulse generated by a deflection coil or a flyback coil in the high voltage generation circuit 6 is limited to a predetermined level. This pulse is output at a predetermined peak value with 0V as a reference. Then, FIG. 9B shows a waveform obtained by integrating the FBP by the integrating circuit 7, which is an integral waveform oscillating up and down with reference to the reference potential V _s . Figure 9
The waveform of (c) shows the voltage waveform of the horizontal sync signal output from the horizontal sync separation circuit 2, and FIG.
The bipolar output current waveform of is shown. 9 (e) is shown in FIG.
A bipolar output current waveform of the phase comparator 2 is shown as in (d), but it is a transient operation waveform of the output of the phase comparator 2 when the phase of the FBP advances.

The phase comparator 2 temporarily generates a current pulse I _s synchronized with the horizontal synchronizing signal (c) input from one input terminal in the circuit. Then, with the intersection with the reference potential V _s indicated by the chain double-dashed line in FIG. 9B as a boundary, the output current is set to a negative polarity during the upper half-wave of the integrated waveform (the period from intersection A to B), and A bipolar current pulse having a positive output current is output during the side half-wave (the period from the intersection point B to the point C) (see FIG. 9D).

The filter 3 smoothes the bipolar output current of the phase comparator 2 and outputs a phase error voltage V _e according to the averaged DC current. VCO4 connected to its output
The filter 3 oscillates at a frequency corresponding to the level of the phase error voltage V _e of the output. The phase of FBP is the horizontal synchronization signal (c)
The flyback pulse is FBP,
₁ (indicated by the solid line in FIG. 9 (a)), the integrated waveform becomes an integrated waveform S ₁ indicated by the solid line in FIG. 9 (b). At this time, the bipolar output current of the phase comparator 2 is (
As in (d)), yet the same width are output by the positive pulse and a negative pulse of the same amplitude, the phase error voltage V _e of the output of the filter 3 becomes zero.

Next, the flyback pal is caused by some factors.
FBP₂ Phase (as shown by the broken line in Fig. 9 (a))
Is t₁ If only the
(B) integrated waveform S₂ Like t₁ Advanced, integrated waveform
The crossing point of goes from the initial b to the output of the phase comparison circuit 2
The pulse width on the negative polarity side of the pulse is as shown in FIG. 9 (e).
Transiently widens. Then, according to the
Output phase error voltage V_eBecomes a negative potential. As a result,
Phase error voltage V of the output of filter 3_e According to VCO4
Oscillation frequency becomes low, and FBP₂ Is delayed in phase. That
And the FBP coincides with the phase of the horizontal sync signal,
Returning to the state of the solid line in (a), the phase error voltage V _e Is again
Return to zero. On the contrary, when the phase of FBP is delayed, the positive polarity
The pulse width on the side widens transiently and this time
Phase error voltage V of output of filter 3_e Becomes positive potential.
Then, the phase error voltage V_e Oscillation frequency of VCO4 according to
The number becomes higher and the phase of FBP is advanced.
Returning to the state of the solid line, the phase error voltage V_e Becomes zero again
It In this way, the horizontal AFC circuit is horizontally synchronized with the FBP.
Oscillate the VCO 4 while matching the phase with the signal
It

[0009]

However, in the above-mentioned conventional structure, the period during which the FBP is generated in the high voltage generating circuit 6 corresponds to the horizontal retrace line period of the image screen, and it may be caused by the setting error of the deflection coil of the image tube. Since the part of the line period is not always displayed at the proper position on the screen, the phase difference between the FBP and the horizontal synchronizing signal is adjusted, and the blanking period (FBP) is set at the proper position on the screen. There must be. recent years,
These signal processing circuits are being integrated into ICs, the places where external terminals are provided are quite limited, and the places where large capacitances are connected are often used as external terminals.

Then, the means for adjusting the phase of the FBP studied in the horizontal AFC circuit made into an IC will be described below. Figure 1
Reference numeral 0 is a circuit diagram of adjusting means when the conventional AFC circuit shown in FIG. 8 is integrated into an IC. 10, the same parts as those in FIG. 8 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 10, 8 to 13 are transistors, R1 to R5 are resistors, and R
_v is a semi-fixed variable resistor, C ₁ and C ₂ are capacitors, V ₁ and V _s
Is a voltage source for bias, V _cc is a power supply voltage terminal, 14 is a constant voltage diode, 15 is a frame representing an IC integrated part,
Reference numeral 16 is an external terminal of the IC, and 17 is an input terminal for a horizontal synchronizing signal.

Resistance R₁ And the constant voltage diode 14 are high voltage
The voltage level of the FBP output from the generation circuit 6 is set to a predetermined level.
It is a circuit that limits to a bell. The integrating circuit 7 has a resistor R₂ And
Quantity C ₁ Composed by. Then, the phase comparator 2
To have active loads 12 and 13 in the collector circuit.
A differential circuit 18 composed of the transistors 10 and 11;
Current pulse generation that generates a flow pulse and gives it to the differential circuit 18
Means (transistors 8, 9 and resistor R_Five And voltage source V
₁ ) And.

Next, the circuit operation of FIG. 10 will be described with reference to FIG. 11A to 11F are shown in FIG.
FIG. 7 is an operation waveform diagram for explaining the operation of the conventional horizontal AFC circuit shown in FIG. FIG. 11A shows a waveform in which the FBP from the high voltage generating circuit 6 is limited to a predetermined level.
11B shows an integral waveform obtained by integrating the FBP (FIG. 11A) by the integrating circuit 7, and FIG. 11C shows the input terminal 17
11 shows the voltage waveform of the horizontal synchronizing signal input from
(D) shows the bipolar output current waveform of the phase comparator 2. Note that FIG. 11E shows a bipolar output current waveform of the phase comparator 2 similarly to FIG. 11D, and phase comparison when the resistance value of the resistor R _v becomes large and the voltage drop V _r becomes large. 3 shows a transient operation waveform of the output of the device 2. And FIG.
(F) shows the finally stabilized phase of the integrated waveform.

The phase comparator 2 comprises current pulse generating means (transistors 8 and 9, resistor R ₅ and voltage source V ₁ ) and a differential circuit 18, and the current pulse generating means for generating the current pulse I _s is an input terminal. Transistor 8 performs a switching operation according to a horizontal synchronizing signal (see FIG. 11C) input from 17 and has a bottom of zero and a peak value determined by the bias voltage of voltage source V ₁ and resistor R ₅ . The generated current pulse I _s is generated in synchronization with the horizontal synchronizing signal.

On the other hand, the differential circuit 18 has active loads 12 and 13 in the collector circuit, and resistors R ₃ and R _{3 in} both bases.
Differential pair transistor 1 to which a predetermined bias voltage V _s (corresponding to V _s in FIG. 11B) is applied via R ₄ .
1 and 10 and the output of the current pulse generating means (transistor 9
A current pulse I _s is provided from the collector of the current source). Further, the input signal obtained by integrating the FBP is input to the base of the transistor 10 via the coupling capacitance C ₂ . And
The differential circuit 18 switches the polarity of the current pulse I _s between positive polarity and negative polarity with the upper half wave and the lower half wave of the integrated waveform, and outputs the bipolar output current to the filter 3.

A variable resistance R _v connected in series with the capacitance C _1.
Is used for phase adjustment, and when the variable resistance R _v is zero, it operates similarly to the conventional AFC circuit shown in FIG. That is, in FIG. 10, when the variable resistance R _v is zero,
The FBP indicated by the solid line in (a) is input to the integrator circuit 7, the output of the integrator circuit 7 becomes the state of S _{1 in} FIG. 11 (b), and the output of the differential circuit 18 is bipolar in FIG. 11 (d). Output the output current.

Next, the operation when the resistance value of the variable resistor R _v is increased will be described. Increasing the resistance value of the variable resistor R _v, the voltage drop V _r of the variable resistor R _v is superimposed on the integrated waveform. Now, assuming that the voltage drop V _r is superposed on the integrated waveform, as shown in FIG.
If the state of S ₂ shown by the solid line in 1 (b) is reached, the intersection of the reference potential V _s and the integral waveform advances from a to e, and the negative polarity pulse of the bipolar output current of the output of the differential circuit 18 is output. The width becomes wider as shown in FIG. 11E, and the phase error voltage V _e
Becomes a negative voltage. As a result, the oscillation frequency of the VCO 4 becomes transiently low and the phase of the FBP is delayed. Then, the phase of the integrated waveform is gradually delayed, and the intersection e in FIG.
The pulse width of the bipolar current pulse of the output of the differential circuit 18 is balanced and the pulse widths of the positive polarity and the negative polarity are balanced, and the phase change of the FBP is stopped.

In the above description, the voltage drop V _r is momentarily increased for the sake of easy understanding of the operation. However, if the resistance value of the variable resistor R _v is manually adjusted, The duty of the bipolar output current is slightly changed, and the FB is changed in accordance with the change of the variable resistance R _{v while} the waveform of the bipolar output current of FIG.
The phase of P can be adjusted smoothly.

In any case, the above-mentioned means has a problem that the phase of the FBP can be adjusted only in one direction with respect to the horizontal synchronizing signal and further in a direction in which the FBP phase is delayed.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a horizontal AFC circuit in which the phase of the flyback pulse (FBP) can be adjusted forward and backward with respect to the horizontal synchronizing signal.

[0020]

In order to achieve this object, a first horizontal AFC circuit of the present invention comprises a filter, a VCO, a horizontal deflection output circuit, a high voltage generating circuit, an integrating circuit, from the output of a phase comparator. A horizontal AF that forms a loop that returns in the order of input of the phase comparator and synchronizes the FBP with the horizontal synchronization signal.
In the C circuit, the phase comparator has a differential load transistor in which the collector circuit has an active load and a predetermined potential is applied to both bases via the first and second resistors,
Both a current pulse generating means for applying a current pulse synchronized with the horizontal synchronizing signal to the emitter coupling point of the differential pair transistor, and a current which is connected to one end of the first resistor and is adjustable in both positive and negative polarities. The output signal of the integrating circuit is input to one of the base inputs to which the second resistor is connected.

Next, the second horizontal AFC circuit of the present invention is
In the horizontal AFC circuit that forms a loop that feeds back from the output of the phase comparator in the order of the filter VCO, the horizontal deflection output circuit, the high voltage generation circuit, the integration circuit, and then the input of the phase comparator, and synchronizes the FBP with the horizontal synchronization signal, The integrating circuit has a CR series circuit composed of an integrating capacitor and a third resistor, and the phase comparator has an active load in the collector circuit and a predetermined value in both bases via the first and second resistors. A differential pair transistor to which a potential is given, a current pulse generating means for giving a current pulse synchronized with a horizontal synchronizing signal to an emitter coupling point of the differential pair transistor, and a current source connected to one end of the first resistor for giving a current. And a voltage between the terminals of the CR series circuit is input to one of the base inputs to which the second resistor is connected.

Next, the third horizontal AFC circuit of the present invention is
In addition to the configuration of the second horizontal AFC circuit of the present invention, it has a configuration in which a current source that supplies a current to one end of the first resistor performs a switching operation in synchronization with the FBP.

[0023]

With the above construction, in the first invention,
The potential of the reference input is changed up and down by the bidirectional current source, and the intersection of the reference input potential and the integrated waveform is moved according to the up and down movement of the reference potential V _s , and the phase of the FBP is arbitrarily set before and after the horizontal synchronizing signal. Can be set.

In the second invention, the phase of the FBP can be adjusted in one direction by adjusting the resistance value of the CR series circuit, and the phase of the FBP can be adjusted in the opposite direction by setting the current of the current source.

In the third invention, the same operation as in the second invention is performed, but since the current source performs the switching operation in synchronization with FBP, the potential of the reference input is level-shifted in synchronization with FBP. , The phase of the FBP can be adjusted even in a range exceeding the pulse width of the FBP, and the phase of the FBP can be adjusted in a wide range.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A horizontal AFC circuit according to an embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram of a horizontal AFC circuit according to a first embodiment of the present invention. In FIG. 1, 2 is a phase comparator that detects a phase error between the horizontal synchronizing signal and FBP, and outputs a bipolar output current weighted in positive polarity and negative polarity, and 3 is a smooth output current of the phase comparator 2. The filter 4 is a VCO that varies the oscillation frequency according to the DC output voltage of the filter 3, 5 is a horizontal deflection output circuit that amplifies the output of the VCO 4, 6 is a deflection coil, a flyback coil, or the like. A high voltage generating circuit for generating FBP, 7 is an integrating circuit for integrating FBP, 8 to 13
Is a transistor, 14 is a constant voltage diode, 17 is a horizontal synchronizing signal input terminal, 18 is a differential circuit, 19 to 22 are transistors, 23 is a current source, V ₁ , V ₂ and V _s are bias voltage sources, V _cc is the power supply voltage terminal, R ₁ to R ₇ are resistors, C _1, C ₂ is the capacitance. The current pulse generating means is
It is composed of transistors 8 and 9, a resistor R ₅ and a voltage source V _1, and the bias voltage of the voltage source V ₁ is applied to the base of the transistor 9 so that the emitter potential of the transistor 9 is almost fixed and the input is applied. The horizontal synchronizing signal supplied from the terminal 17 causes the transistor 8 to perform a switching operation. Then, the crest value of the current is determined by the resistor R ₅ , and the current pulse I _s generated in synchronization with the horizontal synchronizing signal is generated, and the current pulse I _s is generated by the differential pair transistors 10 and 1.
One is given to the emitter coupling point.

The bidirectional current source has the active loads 21 and 22 in the collector circuit and the current source 2 at the emitter coupling point.
3 is connected to the differential pair of transistors 19 and 20, the base of the transistor 19 is biased by the voltage source V _s , and the voltage source V connected to the base of the transistor 20.
Controlled by ₂ . The polarity and absolute value of the output current depends on the voltage source V
It is controlled by the control voltage of ₂ and applies an output current from the output end of the active load (collector of the transistor 22) to one end of the first resistor R ₃ . The differential pair transistor 1
Resistors R ₆ and R ₇ provided in the emitter circuits of 9 and 20
When the resistance value is increased, the gradient of the change amount of the output current with respect to the change amount of the control voltage V ₂ becomes small, and the output current of the bidirectional current source can be finely adjusted. In this embodiment, the one based on the differential circuit 18 is used, but a bidirectional current source can be configured even by combining positive and negative current sources and fixing one and varying the other. A bidirectional current source can be configured even if both are variable at the same time.

The phase comparator 2 has active loads 12 and 13 in the collector circuit and resistors R in both bases.
_A differential circuit 1 including a differential pair transistor 11 and 10 to which a predetermined bias voltage V _s is applied via ₃ and R _4.
8, a current pulse generating means, and a bidirectional current source (composed of transistors 19 to 22), the output signal of the integrating circuit 7 is input to the base of the transistor 10 via the coupling capacitance C ₂ . Then, the differential circuit 18 switches the polarity of the current pulse I _s between positive polarity and negative polarity by the upper half wave and the lower half wave of the integrated waveform, and the output current of both polarities is filtered by the filter 3.
Output to.

The horizontal AFC circuit according to the first embodiment includes the output terminal of the phase comparator 2, the filter 3, the VCO 4,
A path is drawn in the order of the horizontal deflection output circuit 5, the high voltage generation circuit 6, the integration circuit 7, and the input terminal of the phase comparator 2 to form a feedback loop of the AFC.

Next, the operation of the horizontal AFC circuit thus constructed will be described with reference to the operation waveform diagram of FIG. FIGS. 2A to 2F are operation waveform diagrams for explaining the operation of the horizontal AFC circuit in the first embodiment of the present invention. FIG. 2A shows the waveform of the FBP in which the high voltage pulse output from the high voltage generating circuit 6 is limited to a predetermined level by the limiting circuit composed of the resistor R ₁ and the constant voltage diode 14. The solid line shows the state when the phases of FBP ₁ and the horizontal synchronizing signal match. The broken line is the resistance R ₃
As a result of applying a current to the resistor R ₃ to generate a voltage drop V _x between the terminals of the resistor R ₃ , the phase of FBP ₂ is advanced with respect to the horizontal synchronizing signal.

FIG. 2B shows an FBP ₁ by the integrating circuit 7.
2 shows a waveform S ₁ obtained by integrating (shown in FIG. 2A).
(C) shows the voltage waveform of the horizontal sync signal output from the horizontal sync separation circuit 2. The current pulse of the current pulse generating means is also generated in synchronization with this horizontal synchronizing signal. Figure 2
(D) shows the waveform of the bipolar output current of the phase comparator 2 when the horizontal synchronizing signal and the FBP are synchronized. Figure 2 (e) shows
Similar to FIG. 2D, a waveform of the bipolar output current of the phase comparator 2 is shown, but a transient operation waveform of the output of the phase comparator 2 when the phase of the FBP advances is shown. FIG. 2F shows the finally stabilized phase of the integrated waveform.

Current generating means (transistor) in the phase comparator 2
Stars 8 and 9 and resistance R_Five ) Is input from the input terminal 17
Signal in response to the horizontal synchronizing signal (shown in FIG. 2 (c)).
Flow pulse I_s To generate. Also, a bidirectional current source (trans
If the output current of transistors 19 to 22) is zero,
The bases of the differential pair transistors 10 and 11 are the reference potential V. _s 
Biased to a potential equal to. And the coupling capacitance C
₂ The integrated waveform (shown in Fig. 2 (a)) is
When input to the base of the controller 10, the current pulse I _s Is the base
Reference the quasi-input potential (base potential of transistor 11)
And the upper half wave and lower half wave of the integrated waveform input
The conduction between the transistors 10 and 11 is switched alternately to change the phase ratio.
Both poles at the output end of the comparator 2 (collector of the transistor 10)
Output as a positive output current. That is, in FIG.
Reference potential V shown by the dotted line_s The current pulse at the intersection with
I_s Switch the polarity of the
The period from (1) to (2), the output current becomes negative and
Positive output current when half-wave (interval B to C)
Output bipolar output current (see Fig. 2 (d)).
See).

Next, the filter 3, a bipolar output current of the phase comparator 2 is smooth, and outputs a phase error voltage V _e corresponding to the phase difference between the FBP and the horizontal synchronizing signal. This phase error voltage V _e becomes zero if there is no phase difference between the FBP and the horizontal synchronizing signal (when the pulse widths of the positive polarity pulse and the negative polarity pulse of the bipolar output current are equal), and becomes the horizontal synchronization signal. On the other hand, when the phase of the FBP advances, a negative error voltage is output, and conversely, when the phase is delayed, a positive error voltage is output.

[0035] Then, VCO 4 oscillates at a frequency corresponding to the level of the phase error voltage V _e of the output of the filter 3. F
BP is synchronized with the oscillation output of VCO4,
When the phase is in agreement with the horizontal synchronizing signal, the flyback pulse has a solid line FBP ₁ in FIG. 2A and its integrated waveform has a solid line S _{1 in} FIG. 2B. At this time, as for the bipolar output current of the phase comparator 2, as shown in FIG. 2 (d), the positive polarity pulse and the negative polarity pulse of the same width are output vertically symmetrically, and the output of the filter 3 averages them and outputs the DC voltage. and outputs a phase error voltage V _e, the phase error voltage V _e at this time is zero. Then, the AFC loop outputs a negative phase error voltage V to the output of the filter 3 when the phase of the FBP advances, for example.
By outputting _e , the oscillation frequency of the VCO 4 is lowered to delay the phase of the FBP. On the contrary, when the phase is delayed, the oscillation frequency of the VCO 4 is increased and the phase is advanced. In this way, the horizontal AFC circuit controls the oscillation frequency of the VCO 4 so that the FBP phase matches the horizontal synchronization signal.

Next, the phase adjustment of the FBP will be described. For example, when advancing the phase of FBP, voltage source V ₂
Is set higher than the reference voltage source V _s, and a current is caused to flow from the transistor 22 to the resistor R ₃ to cause a positive voltage drop across the resistor R ₃ . When the voltage drop is V ₃ , the potential of the comparison input of the differential circuit 18 (base potential of the transistor 11) rises to (V _s + V ₃ ). Then, the switching point of the bipolar output current switched by the phase comparison circuit 2 is the intersection point a when the output current of the bidirectional current source is zero,
What was B and C moved to intersections C, R, and N as the reference input potential increased. Then, if this potential is instantaneously moved, the waveform of the bipolar output current becomes narrower in the width of the current pulse on the negative side as shown in FIG. 2 (e), and the positive phase error voltage V Output _e . Then, when the oscillation frequency of the VCO 4 becomes high in accordance with the positive phase error voltage V _e , the phase is advanced from FBP ₁ to FBP _2, and the positive polarity side pulse and the negative polarity side pulse of the bipolar output current are balanced. The phase of the FBP is advanced to, the intersection of the potential of the reference input and the integrated waveform advances to Fig. 2 (f), and the positive polarity side pulse and the negative polarity side pulse of the bipolar output current are shown in Fig. 2.
The phase transition is stopped in balance as in (d). In the above description, in order to facilitate understanding of the operation, the operation when the potential of the reference input is momentarily increased has been described. However, in the operation setting in which the voltage source V ₂ is manually changed, the reference input is slowly changed. The phase of the FBP can be adjusted in a state in which the duty of the bipolar output current is hardly broken by following the potential change.

[0037] Conversely, if the delay the phase of the FBP sets the voltage source V ₂ lower than the reference voltage source V _s, draws current from the resistor R ₃ from the transistor 22, a negative voltage drop across the resistor R ₃ It should be generated. Then, the oscillation frequency of the VCO 4 decreases according to the negative phase error voltage V _e ,
The phase of the FBP moves in the direction of delaying, and the phase transition is completed in a state where the positive polarity side pulse and the negative polarity side pulse of the bipolar output current are balanced (shown in FIG. 2D).

As described above, the horizontal AF of this embodiment
In the C circuit, the phase comparator 2 is adjusted by adjusting the bidirectional current source.
The potential of the reference input of is adjusted up and down, the switching operation point (the intersection of the reference input and the integrated waveform) of the positive polarity pulse and the negative polarity pulse of the bipolar output current is changed, and the phase of the FBP is changed to the horizontal synchronization signal. Can be adjusted before and after.

(Second Embodiment) A horizontal AFC circuit according to a second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a circuit diagram of a horizontal AFC circuit according to the second embodiment of the present invention. In FIG. 3, reference numeral 2 denotes a phase comparator that detects a phase error between the horizontal synchronizing signal and the FBP, and outputs a bipolar output current weighted with positive polarity and negative polarity, and 3 smoothes the output current of the phase comparator 2. Filter,
Reference numeral 4 is a VCO that varies the oscillation frequency according to the DC output voltage of the filter 3, reference numeral 5 is a horizontal deflection output circuit that amplifies the VCO output, and reference numeral 6 is a high voltage that is composed of a deflection coil, a flyback coil or the like and that generates a high voltage FBP. Generator circuit, 7 is FBP
An integrating circuit that integrates, 8 to 13 are transistors, 14 is a constant voltage diode, 17 is an input terminal for a horizontal synchronizing signal,
24 is a current source, V ₁ and V _s are bias voltage sources, V _cc
Is a power supply voltage terminal, R _{1 to} R ₅ and R ₈ are resistors, C ₁ and C ₂
Is the capacity.

The current pulse generating means is a transistor 8,
9, a resistor R _5, and a voltage source V _1, and the bias voltage of the voltage source V ₁ is applied to the base of the transistor 9 so that the emitter potential of the transistor 9 becomes a substantially fixed potential. The transistor 8 is switched by the applied horizontal synchronizing signal. Then, the peak value of the current is determined by the resistor R ₅ , and a current pulse I _s synchronized with the horizontal synchronizing signal is generated, and the current pulse I _s is given to the emitter coupling points of the differential pair transistors 10 and 11.

Next, the phase comparator 2 has active loads 12 and 13 in the collector circuit, and resistors R ₃ and R _{3 in} both bases.
A differential circuit 18 including a differential pair transistor 11 and 10 to which a predetermined bias voltage V _s is applied via R _4.
Then, the output signal of the current pulse generating means and the integrating circuit 7 is input to the base of the transistor 10 via the coupling capacitance C ₂ . Then, the differential circuit 18 switches the current pulse between positive polarity and negative polarity by the upper half wave and the lower half wave of the integrated waveform, and outputs the bipolar output current to the filter 3. However,
Reference input of phase comparator 2 (base of transistor 11)
Is different from the first embodiment in that the bias voltage can be changed by supplying the current from the current source 24.

The integrating circuit 7 has a resistor R in series with a capacitor C _1.
Unlike the first embodiment in that ₈ is added, the capacitance C ₁
The voltage between the terminals of the series circuit of the resistor R ₈ and the resistor R ₈ is applied to the comparison input (base of the transistor 10) of the phase comparator 2.

The horizontal AFC circuit according to the second aspect of the invention comprises the output terminal of the phase comparator 2, the filter 3, the VCO 4,
A path is drawn in the order of the horizontal deflection output circuit 5, the high voltage generating circuit 6, the integrating circuit 7, and the input terminal of the phase comparator 2 to form an AFC feedback loop as in the first embodiment.

Next, the horizontal AFC circuit constructed as described above is used.
The operation of the road will be explained with reference to the operation waveform diagram of FIG.
Reveal 4 (a) to 4 (f) are horizontal AFC times shown in FIG.
It is an operation waveform diagram for explaining the operation of the road. Figure 4
(A) shows the high voltage pulse output from the high voltage generation circuit 6.
Resistance R ₁ And a limiting circuit consisting of a constant voltage diode
It is the waveform of FBP limited to a predetermined level by. Fruit
Wire has a suitable resistance R₈ The capacity C₁ Insert in series with FBP
₁ Indicates that the phase of is delayed with respect to the horizontal sync signal.
You And the broken line is the resistance R₃ The current from the current source 24
Give resistance R₃ Voltage drop V between terminals_x Which caused
Fruit FBP₂ The phase of has advanced with respect to the horizontal sync signal.
Show.

FIG. 4B shows the FBP by the integrating circuit 7.
₁ Waveform S obtained by integrating (see FIG. 4A)₁ Indicates. First
The integrating circuit (indicated by 7 in FIG. 1) used in the first embodiment is a resistor.
R₂And capacity C₁ , And simply integrates the FBP waveform
Triangular wave capacity C₁ It outputs between the terminals of
(See FIG. 2B), integrating circuit used in the second embodiment
7 is capacity C₁ In series with resistor R₈ Connected in series
The voltage between the terminals of the path is input to the phase comparator 2. for that reason
The input signal of the phase comparator 2 is the peak value V of the FBP. _p To
Anti-R₂ And resistance R₈ Resistance R when divided by₈ Between terminals
Voltage (square wave) and capacity C₁ And resistance (R₂ + R₈ ) With
The waveform is the sum of the triangular wave integrated with a constant.

FIG. 4C shows the output from the horizontal sync separation circuit 2.
The voltage waveform of the applied horizontal sync signal
Current pulse I generated by raw means_s This horizontal sync signal
It is generated in synchronization with. In addition, the current of the current source 24 is zero
If so, the bases of the differential pair transistors 10 and 11 are reference
Potential V_s Is biased to a potential equal to ₂ 
The integrated waveform (see Fig. 4 (a)) is
When input to the base of 10, the current pulse I_s Is the standard
Based on the input potential (base potential of transistor 11)
Then, the upper half wave and the lower half wave of the integrated waveform input
The phase comparator 2 by alternately switching the conduction between the data 10 and 11
Output to the output terminal (collector of transistor 10)
Output as current. That is, the two-dot chain line in FIG.
Reference potential V_s Current pulse I at the intersection with_s 
The polarity of the integrated waveform is switched to the upper half wave of the integrated waveform (
Period) until the output current becomes negative and the lower half wave
The output current is positive when
Output a bipolar output current (Fig. 4 (b) and
(See (d)).

FIG. 4D shows the waveform of the bipolar output current of the phase comparator 2 when the horizontal synchronizing signal and the FBP are synchronized with each other in phase. In addition, FIG.
Similar to (d), the waveform of the bipolar output current of the phase comparator 2 is shown, but it is a transient operation waveform of the bipolar output current of the phase comparator 2 in the process of the phase advance of the FBP. Also, FIG. 4 (f)
Shows the phase of the finally stabilized integrated waveform.

In the method of adjusting the phase of the horizontal AFC circuit in the second embodiment, the maximum delay phase within the variable range desired by the FBP with respect to the horizontal synchronizing signal is first set with the current value of the current source 24 set to zero. The resistance value of the resistor R ₈ is preset so that When the voltage drop V _r of the resistor R ₈ becomes large, the rising of the integrated waveform becomes faster according to the magnitude thereof, and the phase of FBP with respect to the horizontal synchronizing signal is delayed like the operation waveform of the conventional horizontal AFC circuit shown in FIG. Can be synchronized. The solid line FBP ₁ in FIG.
The operation waveforms of (b), (c), and (d) show a state in which the phase of the FBP is delayed and synchronized. At this time, assuming that the pulse width of the horizontal synchronizing signal is t as shown in FIG. 4C, the bipolar output current has a positive pulse width of t / 2 and a negative polarity as shown in FIG. 4D. The pulse width is stabilized at a pulse width of t / 2.

Next, a current is made to flow from the current source 24 to the resistor R ₃ to raise the potential of the reference input (base of the transistor 11). Then, similarly to the first embodiment described above, in accordance with the rise of the reference input potential (V _s + V ₃ ), the bipolar output current switching operation point of the phase comparator 2 (reference input and integrated waveform 4) is set to the rear of FBP ₁ (the intersection Y in FIG. 4 (b)), and the positive polarity side of the bipolar output current of the phase comparator 2 is transiently wide as shown in FIG. 4 (e). And the phase of FBP is advanced. Then, when the phase of the integrated waveform advances and reaches the position where the crossing point Y in FIG. 4B corresponds to the center point of the horizontal synchronizing signal, that is, the position of the crossing point S0 in FIG. 4F, the bipolar output current changes. Figure 4 (d)
Returning again to the operation waveform of, the relative position between the FBP and the horizontal synchronizing signal is fixed, and the FBP and the horizontal synchronizing signal oscillate in synchronization. That is, the resistor R ₈ functions to delay the phase of the FBP, the voltage drop V _r of the resistor R ₃ functions to advance the phase of the FBP, and as a result, the phase of the FBP can be adjusted before and after the horizontal synchronizing signal.

In the second embodiment, the larger the resistance value of the resistor R ₈ and the larger the voltage drop V _r , the later the phase of the FBP can be delayed, but the gradient of the triangular wave component is small. Therefore, when noise is mixed, chattering is likely to occur in the output current of the phase comparator 2, so it is not preferable to make the resistance R ₈ extremely large. The magnitude of the voltage drop V _r generated in the resistor R ₈ is 1/4 of the amplitude of the integrated waveform.
It is preferable to set the degree to the maximum value.

Further, in the second embodiment, the phase is delayed in advance by setting the resistance R ₈ , and the current value of the current source 24 is changed to adjust the phase so as to advance the phase. As a result, the phase of the FBP is adjusted before and after the horizontal synchronizing signal. However, it is needless to say that the same effect can be obtained even if the phase is advanced in advance by setting the current source 24 and the resistance R ₈ is changed so as to delay the phase.

As described above, in the second embodiment, F
The phase of BP can be adjusted before and after the horizontal sync signal,
When the potential (V _s + V ₃ ) of the reference input becomes high and the period T ₁ of the upper half wave of the integrated waveform becomes smaller than t / 2, the horizontal A
The FC loop phase adjustment fails. That is, F
Even if the phase of the BP can be adjusted back and forth, the FBP center can be slightly adjusted with respect to the center of the horizontal sync signal within the range in which the horizontal sync signal is completely included in the pulse width of the FBP. It was in the range. To solve this point,
The third embodiment, which will be described next, further expands the adjustment range of the FBP.

(Third Embodiment) A horizontal AFC circuit according to a third embodiment of the present invention will be described below with reference to FIG. FIG. 5 is a circuit diagram of a horizontal AFC circuit according to the third embodiment of the present invention. In FIG. 5, the same parts as those of the second embodiment shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. Differences from the second embodiment will be described. In FIG. 5, 8 to 13 and 25 to 29 are transistors, R _{2 to} R ₅ , R ₈ and R ₉ are resistors, 30 is a variable current source, 31 is a current source, and 32 is a bias voltage source.

As shown in FIG. 5, the transistors 27 and 28 constituting the differential circuit compare the FBP signal with the bias voltage source 32 as a reference to perform switching operation of the output current of the variable current source 30, thereby causing the transistors 25 and 28 to operate. Variable current source 30 mirror-inverted via a current mirror composed of 26
Output current of the phase comparator 2 reference input (transistor 1
1 base). The voltage value of the bias voltage source 32 is preferably at a level about 1/2 of the peak value V _p of the FBP.

As described above, the third embodiment is different in that it corresponds to the current source 24 in the second embodiment and is configured to perform the switching operation in synchronization with the potential of the reference input in FBP. .

Next, the operation of the horizontal AFC circuit thus configured will be described with reference to the operation waveform diagram of FIG. FIG 6 (a) ~ (f) is an operation waveform diagram for explaining the operation of the horizontal AFC circuit shown in FIG. 5, the resistor R ₃
7 shows an operation waveform when the voltage drop V ₃ is extremely increased.

FIG. 6A shows the waveform of the FBP in which the high voltage pulse output from the high voltage generating circuit 6 is limited to a predetermined level by the limiting circuit composed of the resistor R ₁ and the constant voltage diode 14, and FIG. ) Is FBP by the integration circuit 7.
6 shows a waveform S obtained by integrating (see FIG. 6A).
6C shows the voltage waveform of the horizontal synchronizing signal input from the input terminal 17, and FIG. 6D shows the waveform of the bipolar output current of the phase comparator 2. The current pulse I _s generated by the current pulse generating means is also generated in synchronization with this horizontal synchronizing signal.

In the horizontal AFC according to the third embodiment, the transistors 27 and 28 forming the differential circuit compare the FBPs with the bias voltage source 32 as a reference to perform switching operation of the output current of the variable current source 30 to make the FBP. The current of the variable current source 30 is applied to the reference input (base of the transistor 11) of the phase comparator 2 only when is input. Then the voltage drop V ₃ of the resistor R ₃ is generated synchronously with FBP, the phase comparator 2
The electric potential of the reference input of is switched to two electric potentials of reference electric potentials V _s and (V _s + V ₃ ) as indicated by the chain double-dashed line in FIG. 6B. Then, when the integrated waveform S is input to the base of the transistor 10, the current pulse I _s has a potential of the reference input (see FIG. 6).
The conduction of transistors 10 and 11 is alternately switched between the upper half wave and the lower half wave of the integrated waveform input with reference to the chain double-dashed line in (b), and the output terminal of the phase comparator 2 (transistor 10) is switched.
Output a bipolar output current. That is,
When the integrated waveform becomes a high potential at the intersection (T, N, NA, LA, M) of the reference input potential and the integrated waveform S shown by the chain double-dashed line in FIG. And the output current is negative during the period from the intersection Na to LA) and the output current is positive when the integrated waveform has a low potential (the period from the intersection LA to M). The phase comparator 2 outputs.

The method of adjusting the phase of the horizontal AFC circuit in the third embodiment is basically the same as that in the second embodiment. In the third embodiment, spike noise n is generated in the bipolar output current when (V _s + V ₃ ) is increased to near the peak value of the integrated waveform. This phenomenon occurs because both the differential pair transistors 10 and 11 become conductive because the reference input and the integral waveform match between (the intersection point N and the intersection point N).
This phenomenon is by no means preferable, but (V _s +
In the range until the potential of V ₃ ) reaches the peak value of the integral waveform, the intersection changes along the rising slope of the integral waveform, and the negative pulse is operated even during the period from the intersection Na to the intersection LA. Therefore, there is no problem. The extreme state of the operation of the third embodiment is the peak value of the integrated waveform and (V _s + V
₃ ) and the horizontal sync signal does not cause a problem even if the horizontal sync signal extends by the amount of the negative polarity pulse in the range from intersection point a to intersection point la. Therefore, as shown in FIG. Is t, compared to the second embodiment, the FBP is t /
It is possible to make an adjustment that advances by 2 extra.

For reference, when the potential of the reference input is raised to the position (V _s + V ₃ ) shown in FIG. 6 with the circuit configuration of the second embodiment shown in FIG. Since the potential becomes lower than the potential of the reference input, the bipolar output current becomes as shown in FIG. 6 (f). Therefore, the FB in which the positive polarity pulse and the negative polarity pulse should originally be equal to each other
Even phase relationship between P and the horizontal synchronizing signal, it would be further advance the phase of FBP from the components of the positive pulse becomes larger, in the case of the second embodiment shown in FIG. 6 (V _s
FBP phase synchronization and phase adjustment cannot be performed up to a high potential such as + V ₃ ).

(Fourth Embodiment) A horizontal AFC circuit according to a fourth embodiment of the present invention will be described below with reference to FIG. FIG. 7 is a circuit diagram of a horizontal AFC circuit according to the fourth embodiment of the present invention. In FIG. 7, the same parts as those of the third embodiment shown in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. Only the points different from the third embodiment will be described. In FIG. 7, 8 to 13, 33 and 34 are transistors, R _{2 to} R ₅ , R ₈ and R ₉ are resistors, 31 is a current source, 3
Reference numeral 2 is a bias voltage source.

Transistors 33 and 3 forming a differential circuit
4 is F based on the bias voltage of the bias voltage source 32.
BP is compared to switch the current source 31 that supplies current to the common emitter connection point of the transistors 33 and 34,
It is different from the third embodiment shown in FIG. 5 in that the collector current of the transistor 34 is directly applied to the reference input of the phase comparator 2 (base of the transistor 11). In the embodiments other than the third embodiment, the sensitivity converted into the FBP input voltage for switching the current supplied to the reference input terminal becomes worse than that in the third embodiment, which is a little problem, but There is no problem if the input signal level is equal to or higher than the volt, and there is no problem because the FBP limited by the constant voltage diode 14 as in this embodiment has a sufficient amplitude.

The fourth embodiment shown in FIG. 7 is suitable for integration in a semiconductor integrated circuit because the number of elements constituting the circuit is small, and the FB is set in advance by setting the current value of the current source 31.
By advancing the phase of P and adjusting the resistance R ₈ attached externally to delay the phase of FBP, a semiconductor integrated circuit with a minimum number of external terminals can be realized.

The voltage value of the bias voltage source 32 is FB.
The level is preferably about 1/2 of the peak value V _p of _P. Further, in the fourth embodiment, the phase is delayed in advance by setting the resistance R ₈ , and the current value of the current source 31 is changed to adjust the phase so that the phase advances. As a result, the phase of the FBP can be adjusted before and after the horizontal synchronizing signal. However, it is needless to say that the same effect can be obtained even if the phase is advanced in advance by setting the current source 31 and the resistance R ₈ is changed to delay the phase.

[0065]

As described above, the first horizontal A according to the present invention is used.
In the FC circuit, the potential of the reference input is changed up and down by the current supplied from the current source, and the intersection of the reference input potential and the integrated waveform moves according to the vertical movement of the reference input potential.
The phase of FBP can be arbitrarily set before and after the horizontal synchronizing signal.

In the second horizontal AFC circuit according to the present invention, the phase of the FBP can be adjusted in one direction by adjusting the resistance value of the CR series circuit, and the FBP can be adjusted by setting the current of the current source.
The phase of can be adjusted in the opposite direction.

Further, in the third horizontal AFC circuit of the present invention, since the current source performs the switching operation in synchronization with FBP, the potential of the reference input is level-shifted in synchronization with FBP and exceeds the pulse width of FBP. However, the phase of the FBP can be adjusted, and the phase of the FBP can be adjusted in a wide range.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a horizontal AFC circuit according to a first embodiment of the present invention.

2 (a) to (f) are operation waveform diagrams for explaining the operation of the horizontal AFC circuit in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a horizontal AFC circuit according to a second embodiment of the present invention.

4 (a) to 4 (f) are operation waveform diagrams for explaining the operation of the horizontal AFC circuit in the second embodiment of the present invention.

FIG. 5 is a circuit diagram of a horizontal AFC circuit according to a third embodiment of the present invention.

6 (a) to 6 (f) are operation waveform diagrams for explaining the operation of the horizontal AFC circuit in the third embodiment of the present invention.

FIG. 7 is a circuit diagram of a horizontal AFC circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit block diagram of a conventional horizontal AFC circuit.

9 (a) to 9 (e) are operation waveform charts for explaining the operation of the conventional AFC circuit.

FIG. 10 is a circuit diagram of adjusting means when a conventional AFC circuit is integrated into an IC.

11 (a) to (f) are conventional horizontal AFs made into an IC.
Operation waveform diagram for explaining the operation of the C circuit

[Explanation of symbols]

2 Phase comparator 3 Filter 4 VCO 5 Horizontal deflection output circuit 6 High voltage generation circuit 7 Integration circuit 10, 11 Differential pair transistor 12, 13 Active load 14 Constant voltage diode R ₃ First resistance R ₄ Second resistance

Claims (3)

[Claims] 1. A flyback pulse is horizontally generated by forming a loop for feeding back a filter, a voltage controlled oscillator, a horizontal deflection output circuit, a high voltage generating circuit, an integrating circuit, and an input of the phase comparator from the output of the phase comparator. In the horizontal AFC circuit synchronized with the synchronization signal, the phase comparator has an active load in the collector circuit and a differential pair transistor in which a predetermined potential is applied to both bases via first and second resistors, and the difference. Current pulse generating means for applying a current pulse synchronized with the horizontal synchronizing signal to the emitter coupling point of the active-pair transistor, and a current adjustable to both positive and negative polarities, which is connected to one end of the first resistor. A horizontal AFC circuit comprising a bidirectional current source, and an output signal of the integrating circuit is input to one base input to which the second resistor is connected. Road. 2. A flyback pulse is formed horizontally by forming a loop that feeds back from the output of the phase comparator to the filter, the voltage-controlled oscillator, the horizontal deflection output circuit, the high-voltage generating circuit, the integrating circuit, and the input of the phase comparator. In the horizontal AFC circuit synchronized with the synchronizing signal, the integrating circuit has a CR series circuit composed of an integrating capacitor and a third resistor, and the phase comparator has an active load in the collector circuit and both bases. A differential pair transistor to which a predetermined potential is applied via first and second resistors, current pulse generating means for applying a current pulse synchronized with the horizontal synchronizing signal to an emitter coupling point of the differential pair transistor, And a current source connected to one end of the first resistor to supply a current,
C is connected to one base input to which the second resistor is connected.
A horizontal AFC circuit in which a voltage between terminals of an R series circuit is input. 3. The horizontal AFC according to claim 2, wherein a current source for supplying a current is connected to one end of the first resistor, and the switching operation is performed in synchronization with the flyback pulse.
circuit.