JPS6392170A - Vertical synchronizing circuit - Google Patents

Abstract

PURPOSE:To detect a vertical synchronizing signal even at a weak electric field by forming a signal for indicating the detection range of the vertical synchronizing signal from a vertical output pulse and adjusting the time position only of the trailing edge of this signal. CONSTITUTION:When an input 1 is inputted, a transistor TR2 is interrupted when the input 1 goes to low, the collector of the TR2 is opened. Since one of a variable resistance 3 is connected to a power source Vcc, the voltage waveform of a node 9 goes to a signal (b) in an integration circuit consisting of the resistance 3 and a capacitor 4. A comparator 5 compares the inputs at a certain threshold level VTH, at the time of the input lower than the VTH, an output goes to High, on the contrary, at the time of the input higher than it, the output goes to Low. Accordingly, the output has a waveform (c). The waveform (c) and a signal (d) are inputted to an AND circuit 7, thereby, a pulse (e) is outputted to an output terminal 8.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a vertical synchronization circuit used in a television receiver, and in particular, to a vertical synchronization circuit that can detect a vertical synchronization signal without being disturbed by noise even in a weak electric field. related to things.

[Conventional technology]

In recent years, vertical synchronization circuits for television receivers have used circuits that generate vertical output pulses by counting down from horizontal output pulses. When this method is used, if all periods are made detectable when the input vertical synchronizing signal is synchronously separated, the vertical output pulse is disturbed by noise and output when the electric field is weak. To prevent this, the second
As shown in the figure, a countdown circuit generates a pulse 6 whose detection range is the period before and after the expected presence of the vertical synchronization signal, and detection is performed only within this range.

[Problem that the invention seeks to solve]

Therefore, if this range is narrowed, the system will be more resistant to disturbances caused by noise, but the pull-in of vertical synchronization at switch-on or channel switching will become slower. Furthermore, if only the trailing side of the detection range is widened, when no vertical synchronization signal is input, the period of the vertical output pulse is determined by the recent pulse output at the end of the detection range. Therefore, when the vertical synchronizing signal is lost in a weak electric field, the period of the vertical synchronizing signal becomes long, and the vertical synchronization is disturbed, which may cause the screen to blur.

This invention was made in order to solve the problems of the conventional ones as described above, and by changing the synchronization detection range of the vertical synchronization signal, it is possible to prevent vertical synchronization disturbance even when the weak electric irregular vertical synchronization signal is lost. The purpose is to obtain a vertical synchronization circuit that can be eliminated.

[Means for solving problems]

The vertical synchronization circuit according to the present invention has a horizontal output pulse.

Since only the vertical synchronization signal can be varied, the vertical synchronization signal can be detected without being disturbed by noise even in a weak electric field.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of a vertical synchronization circuit according to an embodiment of the present invention. In the figure, 1 is an input, which is a pulse obtained by counting down a horizontal output pulse from a vertical countdown circuit (vertical output pulse generation circuit),
Goes high when the countdown circuit is reset,
A low pulse is input at the start of one period of vertical synchronization. This is, for example, the B standard television system.
In the so-called PAL system, this pulse becomes low at 312.5H from the reset pulse. 2 is an NPN transistor, 3 is a variable resistor, 4 is a capacitor, and 5 is a comparator. 6 is a pulse that becomes H4 in the detection range of the vertical synchronization signal, 7 is an AND circuit, and 20 is a vertical synchronization signal detection range adjustment circuit constituted by each of the above circuits.

Next, the operation will be explained.

Assume that input 1 is input as shown in FIG. Since the transistor 2 enters a cutoff state when the input l becomes low, the collector of the transistor 2 becomes open.

Since one side of the variable resistor 3 is connected to the power supply ■cc,
The voltage waveform at node a becomes a waveform as shown in 9 in FIG. 3 by an integrating circuit including variable resistor 3 and capacitor 4. Comparator 5 compares the inputs at a certain threshold level (vy*), and outputs Hi when the input is lower than 7.4, and outputs Low when the input is high.

Therefore, its output has a waveform as shown at 10 in FIG. By inputting the signal of FIG. 3(d) (same as FIG. 2(b)) together with the comparator output 10 to the AND circuit 7, the pulse 8 of FIG. 3(e) is output to the output terminal 18.
is output to.

In addition, by increasing the three values of variable resistor, it is possible to
Although the rise of the node 9 shown in b) is delayed and the time for the comparator output 10 to change from high to low is delayed, the variable resistor 3. The value of the capacitor 4 may be selected so that the comparator output 1o covers the vertical synchronizing signal detection range 6 as shown in FIG. Furthermore, even if the variable resistor 3 is set to OΩ, the rear side of the detection range of the vertical synchronizing signal will not become shorter than the period of the vertical synchronizing signal, so vertical synchronization will not be lost.

As a result, only the rear side of the detection range of the vertical synchronization signal can be varied, and the period can be varied from a cycle equal to the vertical synchronization signal (8 in FIG. 2) to a cycle equal to the countdown cycle (6 in FIG. 2).

Also, when not using this function, connect node 9 to ground (l
ow).

In the above embodiment, the detection range of the vertical synchronizing signal is varied by changing the variable resistance value.
It goes without saying that the number 4 may be varied and the same function as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the vertical synchronization circuit according to the present invention,
By adding a voltage hold function to the countdown type vertical synchronization circuit, it is possible to vary only the rear side of the detection range of the vertical synchronization signal, which has the effect of reducing disturbances in vertical synchronization during weak electric fields.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a vertical synchronization circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the problems of the conventional vertical synchronization circuit, and FIG. 2(a) is a vertical synchronization signal FIG. 2(C) is a diagram showing pulses indicating the cycle of the vertical synchronizing signal, and FIG. 2(C) is a diagram showing pulses indicating the cycle due to countdown. 3 is a diagram showing the waveforms of each part in FIG. 1, and FIG. 3(a) is a diagram showing the input signal, FIG. ) is a diagram showing the comparator output, Figure 3(e) is a signal waveform diagram showing the detection range of the vertical synchronizing signal,
FIG. 3 is a diagram showing output signals of the circuit shown in the figure. FIG. 4 is a diagram showing the signals of each part in FIG. 1 when the integral constant is changed,
Figure 4 (a) is a diagram showing the input signal of Figure 1, Figure 4 (mountain)
4 is a diagram showing the detection range of the vertical synchronizing signal, and FIG. 4(C) is a diagram showing the comparator output. In the figure, 2 is an NPN) transistor, 3 is a variable resistor,
4 is a capacitor, 5 is a comparator, 7 is an AND circuit,
20 is a vertical synchronization signal detection range adjustment circuit.

Claims (1)

[Claims] (1) A vertical output pulse creation circuit that creates a vertical output pulse by counting down the horizontal output pulse, and creates a signal indicating the detection range of the vertical synchronization signal from the vertical output pulse, and only the trailing edge of the signal and its temporal position. A vertical synchronization circuit comprising: a vertical synchronization signal detection range adjustment circuit for adjusting the vertical synchronization signal detection range.