KR920002108Y1 - Coordinate latching device on display of writepen for crt - Google Patents

Coordinate latching device on display of writepen for crt Download PDF

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Publication number
KR920002108Y1
KR920002108Y1 KR2019860010227U KR860010227U KR920002108Y1 KR 920002108 Y1 KR920002108 Y1 KR 920002108Y1 KR 2019860010227 U KR2019860010227 U KR 2019860010227U KR 860010227 U KR860010227 U KR 860010227U KR 920002108 Y1 KR920002108 Y1 KR 920002108Y1
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South Korea
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output
latch
axis counter
light pen
pulse generator
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KR2019860010227U
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Korean (ko)
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KR880003073U (en
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오세익
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주식회사 금성사
구자학
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Priority to KR2019860010227U priority Critical patent/KR920002108Y1/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/037Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor using the raster scan of a cathode-ray tube [CRT] for detecting the position of the member, e.g. light pens cooperating with CRT monitors

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)

Abstract

내용 없음.No content.

Description

음극선관 단말기용 라이트펜의 화면상 좌표 래치 장치On-screen coordinate latch device for light pen for cathode ray tube terminal

제 1 도는 본 고안의 블록 구성도.1 is a block diagram of the present invention.

제 2 도는 본 고안의 파형정형회로와 래치 펄스발생부의 상세회로도.2 is a detailed circuit diagram of the waveform shaping circuit and the latch pulse generator of the present invention.

제 3a-g 도는 본 고안 회로 각부의 신호파형도.3a-g is a signal waveform diagram of each circuit part of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 파형정형회로 2 : 래치펄스 발생기1: waveform shaping circuit 2: latch pulse generator

4 : X축 계수기 5 : Y축 계수기4: X axis counter 5: Y axis counter

6 : 래치 회로6: latch circuit

본 고안은 음극선관 단말기용 라이트펜(Light Pen)을 화면에 대고 누를 때 작동되는 스위치에 발생되는 펄스를 받아서 라이트펜이 화면의 종축 및 횡축 어느선상에 위치하는가를 파악하는 X-Y좌표를 래치시켜서 출력토록 하는 음극선관 단말기용 라이트펜의 화면상 좌표 래치 장치 구성에 관한 것이다.The present invention receives a pulse generated by a switch that is activated when a light pen for a cathode ray tube terminal is pressed against a screen, and outputs it by latching an XY coordinate that determines which line the vertical pen and the horizontal axis of the light pen are located on. An on-screen coordinate latch device configuration of a light pen for a cathode ray tube terminal.

종래의 음극선관 단말기 화면에 그림을 그릴 때 사용되는 라이트펜은 화면상 임의의 위치에 라이트펜을 위치시켰을 경우 이 라이트펜이 위치하고 있는 좌표를 찾아내야 하므로 이 좌표에 해당하는 소정 데이타를 래치시켰다가 컴퓨터 회로에 공급시켜주는 장치를 필요로 하는 문제점이 있었다.Conventional light pens used to draw pictures on the cathode ray tube terminal screen have to find the coordinates where the light pen is located when the light pen is placed anywhere on the screen. There was a problem of requiring a device for supplying.

따라서 본 고안은 이와같은 점을 감안하여 음극선관 단말기용 라이트펜의 화면상 좌표를 래치하여 공급할 수 있도록 한 라이트펜의 화면상 좌표 래치장치를 제공함을 그 목적으로 하는 것으로서 이하 첨부된 도면을 참조하여 본 고안 장치를 상세히 설명하면 다음과 같다.Accordingly, the present invention has been made in view of the above-described object of the present invention to provide an on-screen coordinate latching device for a light pen capable of latching and supplying on-screen coordinates of a light pen for a cathode ray tube terminal. The device will be described in detail as follows.

먼저 본 고안의 구성은 제 1 도 및 제 2 도에 도시된 바와같이 라이트펜으로부터 펄스신호가 입력되는 저항(101)과 콘덴서(102) 및 반전기(103, 104)로된 파형회로(1)의 출력(A)OR 게이트(203) 및 반전기(204)와 AND게이트(205)로된 래치펄스 발생기(2)에 연결하되, 래치펄스 발생기(2)의 출력(B)은 도트클록 발생기(3)로부터 도트클록(DCLK)이 입력되는 X축 계수기(4)와 수평동기신호(H-syn)가 클록으로 입력되는 Y측 계수기(5)의 계수중지용 제어단자(Co, C1)에 공동 접속하고, X축 계수기(4)와 Y축 계수기(5)의 출력은 인이에이블 출력 단자(OE)가 래치 펄스발생기(2)의 출력(C)에 연결된 래치회로(6)에 연결하여서된 것이다.First, the configuration of the present invention is as shown in Figures 1 and 2 of the waveform circuit 1 composed of a resistor 101, a capacitor 102 and an inverter 103, 104 to which a pulse signal is input from a light pen. Output (A) is connected to a latch pulse generator (2) consisting of an OR gate (203) and an inverter (204) and an AND gate (205), and the output (B) of the latch pulse generator (2) is a dot clock generator (3). ) Is shared with the counter stop control terminals Co and C 1 of the X-axis counter 4 to which the dot clock DCLK is input and the Y-side counter 5 to which the horizontal synchronization signal H-syn is input as a clock. And the outputs of the X-axis counter 4 and Y-axis counter 5 are connected to the latch circuit 6 having the enable output terminal OE connected to the output C of the latch pulse generator 2. will be.

이와같이 구성된 본 고안의 작용효과는 다음과 같다.Effects of the present invention configured as described above are as follows.

우선 제 1 도에서와 같이 파형정형회로(1)는 음극선관 화면상에서 라이트펜의 출력펄스를 받아들여 잡음을 제거하고 디지탈 신호로 파형정형하여 래치펄스 발생기(2)에 가해주게 된다.First, as shown in FIG. 1, the waveform shaping circuit 1 receives an output pulse of a light pen on a cathode ray tube screen, removes noise, and waveforms a digital signal to apply to the latch pulse generator 2.

따라서 래치 펄스발생기(2)는 이 디지탈 신호를 받아들여서 X축 계수기(4)와 Y축 계수기(5)의 계수중지 신호를 출력(B)함과 동시에 래치회로(6)의 인에이블 신호출력을 출력(C)하게 된다.Accordingly, the latch pulse generator 2 receives the digital signal to output the stop signal of the X-axis counter 4 and the Y-axis counter 5 and outputs the enable signal output of the latch circuit 6. Output (C).

즉, X축 계수기(4)와 Y축 계수기(5)에 의해 검색되어진 X, Y좌표에 해당하는 데이타를 래치회로(6)에 래치시켰다가 출력시켜 주게 되는 것이다.That is, data corresponding to the X and Y coordinates retrieved by the X-axis counter 4 and Y-axis counter 5 is latched to the latch circuit 6 and outputted.

이를 제 2 도에 의하여 좀더 상세히 설명하면, 라이트펜을 화면상에 대고 누를 때 동작하는 스위치에 의해 발생되는 소정펄스를 저항(101)과 콘덴서(102)를 잡음제거한 후 반전기(103, 104)를 거쳐서 디지탈 신호(제 3a 도)를 만들어서 래치펄스 발생기(2)를 구성하는 D플립플롭의 클럭단자(CK)에 가해주게 된다.In more detail with reference to FIG. 2, the inverters 103 and 104 are removed after noise is removed from the resistor 101 and the capacitor 102 by a predetermined pulse generated by a switch operated when the light pen is pressed on the screen. Through this, a digital signal (Fig. 3A) is generated and applied to the clock terminal CK of the D flip-flop constituting the latch pulse generator 2.

한편, 수평동기 신호(H-syn)가 OR 게이트(203)를 통해 D 플립플롭(201)의 입력단자(D)에 하이신호(제 3b 도)로 공급되므로 D 플립플롭(201)의 출력은 하이상태가 된다. (제 3d 도) 또한, 도크를록발생기(3)의 출력 (2제 3c 도는 AND 게이트(205)일측에 가해지게 되는데 이때 AND 게이트(205)의 타측 입력(제 3f 도)은 하이상태이므로 AND 게이트(205)의 출력에서는 이 도트클록이 출력(제 3e 도)되어 플립플롭(202)의 클럭단자(CK)에 가해지게 된다.On the other hand, since the horizontal synchronizing signal H-syn is supplied to the input terminal D of the D flip-flop 201 through the OR gate 203 as a high signal (Fig. 3B), the output of the D flip-flop 201 is Goes high. In addition, the dock is applied to the output of the lock generator 3 (second 3c or one side of the AND gate 205), and the other input of the AND gate 205 (higher 3f) is a high state. At the output of the gate 205, this dot clock is output (Fig. 3e) and applied to the clock terminal CK of the flip-flop 202.

따라서 D 플립플롭(202)의 출력(Q)이 하이에서 로우로 반전되는 순간 AND 게이트(205)는 디스에이블되어 더 이상 도트클록 발생기(3)의 출력이 D 플립플롭(202)의 클럭단자(CK)에 입력되지 못하게 되므로 이 D 플립플롭(202)의 출력 (Q : 제 3f 도)이 제 1 도의 X축 계수기(4)와 Y축 계수기(5)의 계수중지용 제어단자(Co, C1)에 가해져서 계수를 종지토록하므로서 라이트펜의 X, Y좌표가 갱정되어진다.As a result, when the output Q of the D flip-flop 202 is inverted from high to low, the AND gate 205 is disabled so that the output of the dot clock generator 3 is no longer the clock terminal of the D flip-flop 202. CK), so that the output (Q: 3f) of this D flip-flop 202 is the count stop control terminals (Co, C) of the X-axis counter 4 and Y-axis counter 5 of FIG. 1 ), the X and Y coordinates of the light pen are adjusted by ending the coefficients.

또한, D 플립플롭(202)의 출력(Q : 제 3g 도)은 로우에서 하이가 되고, 이 신호는 제 1 도에서 래치회로(6)의 인에이블 출력단자(OE)에 가해주므로서 래치회로(6)에 기억되어진 X축 데이타와 Y축 데이타가 출력되게 되는 것이다.In addition, the output of the D flip-flop 202 (Q: FIG. 3g) goes high from low, and this signal is applied to the enable output terminal OE of the latch circuit 6 in FIG. The X-axis data and Y-axis data stored in (6) are outputted.

그리고 본 고안에서 D 플립플롭(201, 202)수직동기신호(V-syn)가 반전기(204)로 반전되어 OR 게이트(203)를 통해 클리어(CLR)에 인가되므로서 플립플롭(201, 202)을 클리어 시키게 되는 것이다.In the present invention, the flip flip flops 201 and 202 are inverted by the inverter 204 and applied to the clear CLR through the OR gate 203. ) Will be cleared.

이상에서와 같이 본 고안에 의하면 간단한 회로구성에 의하여 음극선관 단말기용 라이트펜의 좌표를 구하여 컴퓨터회로에 공급해 줄 수 있는 실용적인 고안인 것이다.According to the present invention as described above is a practical design that can obtain the coordinates of the light pen for the cathode ray tube terminal by a simple circuit configuration and supply to the computer circuit.

Claims (1)

라이트펜으로부터 펄스신호가 입력되는 저항(101)과 콘덴서(102) 및 반전기(103, 104)로 된 파형정형회로(1)의 출력(A)은 D플립플롭(201, 202)과 OR 게이트(203) 및 반전기(204)와 AND 게이트(205)로된 래치펄스 발생기(2)에 연결하되 래치펄스발생기(2)의 출력(B)은 도트클록발생기(3)로부터 도트클록(DCLK)이 입력되는 X축 계수기(4)와 수평동기신호(H-syn)가 클록으로 입력되는 Y축 계수기(5)의 계수중지용 제어단자(Co, C1)에 공동 접속하고, X축 계수기(4)와 Y축 계수기(5)의 출력은 인에이블 출력단자(OE)가 래치 펄스발생기(2)의 출력(C)에 연결된 래치회로(6)에 연결하여서된 음극선관 단말기용 라이트펜의 화면상 좌표 래치장치.The output A of the waveform shaping circuit 1, which is composed of the resistor 101, the capacitor 102, and the inverters 103, 104, to which the pulse signal is input from the light pen, is connected to the D flip-flops 201 and 202 and the OR gate ( 203 and a latch pulse generator 2 having an invertor 204 and an AND gate 205, and the output B of the latch pulse generator 2 is connected to the dot clock DCLK from the dot clock generator 3 by the dot clock generator. The X-axis counter 4 and the horizontal synchronization signal H-syn inputted together are connected to the count stop control terminals Co and C1 of the Y-axis counter 5, which are inputted as a clock, and the X-axis counter 4 And Y-axis counter 5 output the on-screen coordinate latch of the light pen for a cathode ray tube terminal with the enable output terminal OE connected to the latch circuit 6 connected to the output C of the latch pulse generator 2. Device.
KR2019860010227U 1986-07-15 1986-07-15 Coordinate latching device on display of writepen for crt KR920002108Y1 (en)

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KR2019860010227U KR920002108Y1 (en) 1986-07-15 1986-07-15 Coordinate latching device on display of writepen for crt

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Application Number Priority Date Filing Date Title
KR2019860010227U KR920002108Y1 (en) 1986-07-15 1986-07-15 Coordinate latching device on display of writepen for crt

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KR880003073U KR880003073U (en) 1988-04-11
KR920002108Y1 true KR920002108Y1 (en) 1992-03-28

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