KR920004991Y1 - Control circuit of parallel synchronizing signal for flat display - Google Patents

Control circuit of parallel synchronizing signal for flat display Download PDF

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Publication number
KR920004991Y1
KR920004991Y1 KR2019890019215U KR890019215U KR920004991Y1 KR 920004991 Y1 KR920004991 Y1 KR 920004991Y1 KR 2019890019215 U KR2019890019215 U KR 2019890019215U KR 890019215 U KR890019215 U KR 890019215U KR 920004991 Y1 KR920004991 Y1 KR 920004991Y1
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signal
count value
horizontal
control circuit
counter
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KR2019890019215U
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KR910012450U (en
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박오연
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삼성전관 주식회사
김정배
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Priority to JP400936U priority patent/JPH0658673U/en
Priority to DE4040499A priority patent/DE4040499A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • G06F3/1475—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
    • H04N3/233—Distortion correction, e.g. for pincushion distortion correction, S-correction using active elements
    • H04N3/2335—Distortion correction, e.g. for pincushion distortion correction, S-correction using active elements with calculating means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Synchronizing For Television (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

내용 없음.No content.

Description

평판 표시기용 수평 동기신호 제어회로Horizontal Synchronization Signal Control Circuit for Flat Panel Display

제 1 도는 종래의 수평동기신호 제어회로도.1 is a conventional horizontal synchronization signal control circuit diagram.

제 2 도는 본 고안의 수평동기신호 제어회로의 실시예도.2 is an embodiment of a horizontal synchronous signal control circuit of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 카운트값 세팅부 20 : 카운터부10: count value setting unit 20: counter unit

40 : 플립플롭 OR1,OR2: 오아게이트40: flip-flop OR 1 , OR 2 : Oagate

CLK1: 클럭신호 RS1: 제어신호CLK 1 : Clock signal RS 1 : Control signal

HS3: 수평동기신호HS 3 : Horizontal Sync Signal

본 고안은 퍼스털 컴퓨터의 표시장치로 평판표시기로 사용할 경우에 클럭신호에 따라 수평동기신호를 발생시키는 평판표시기용 수평동기신호 제어회로에 관한 것이다.The present invention relates to a horizontal synchronous signal control circuit for a flat panel display that generates a horizontal synchronous signal according to a clock signal when used as a flat panel display as a display device of a personal computer.

퍼스털 컴퓨터들은 기본적으로 CRT 모니터를 표시장치로 사용하도록 구성되어 있으므로 퍼스털 컴퓨터의 표시장치로 평판표시기를 사용할 경우에 평판표시기 전용의 콘트롤러 및 인터페이스회로를 필요로 하게 된다.Since personal computers are basically configured to use a CRT monitor as a display device, when using a flat panel display as a display device of a personal computer, a controller and an interface circuit dedicated to the flat panel display are required.

인터페이스회로는 평판 표시기의 각각의 화소에 소정의 데이타를 지정할 수 있도록 하는 클럭신호를 발생시켜 공급하고, 또한 표시되는 화면이 평판표시기의 중심에 위치되도록 하기 위하여 수평 및 수직 동기신호의 타이밍을 제어하고 있다.The interface circuit generates and supplies a clock signal for assigning predetermined data to each pixel of the flat panel display, and also controls the timing of the horizontal and vertical sync signals so that the displayed screen is located at the center of the flat panel display. have.

이와 같은 인터페이스회로에서 수평동기신호를 제어함에 있어서, 종래의 수평동기신호 제어회로는 제 1 도에 도시된 바와같이, 일정 카운트값을 세팅시키는 스위칭부(11,12), 저항(R1-R16) 및 데이타 셀렉터(13,14)로 된 카운트값 세팅부(10)와, 상기 타운트값 세팅부(10)에 세팅된 카운트값을 로드한 후 클럭신호(CLK1)를 다운카운트하는 카운터(21-23)로 된 카운터부(20)와, 상기 카운터부(20)가 다른 카운트를 완료함에 따라 수평동기신호(HS3)를 출력하는 플립플롭(31,32)으로 된 수평 동기신호 출력부(30)로 구성되었다.In controlling the horizontal synchronization signal in such an interface circuit, the conventional horizontal synchronization signal control circuit, as shown in Figure 1, the switching unit 11, 12 for setting a constant count value, the resistor (R 1- R) 16 ) and a counter for down counting the clock signal CLK 1 after loading the count value setting section 10 including the data selector 13 and 14 and the count value set in the count value setting section 10. 21-23, and a horizontal synchronizing signal output unit comprising flip-flops 31 and 32 for outputting a horizontal synchronizing signal HS 3 as the counter unit 20 completes another count. It consisted of 30.

이와같이 구성된 종래의 수평동기신호 제어회로는 전원 단자(Vcc)에 동작전원이 인가된 상태에서 카운트값세팅부(10)는 선택신호(SEL)에 따라 데이타 셀렉터(13,14)가 스위칭부(11)(12)에 세팅된 일정 카운트값을 선택하여 출력하게 된다.In the conventional horizontal synchronous signal control circuit configured as described above, in the state where the operating power is applied to the power supply terminal Vcc, the count value setting unit 10 has the data selector 13, 14 having the switching unit 11 according to the selection signal SEL. The constant count value set in (12) is selected and output.

이와 같은 상태에서 저전위의 제어 신호(RS1)가 입력되면, 이 저전위의 제어 신호(RS1)가 수평동기신호 출력부(30)의 플립플롭(32)의 프리세트 단자()에 인가되므로 플립플롭(32)을 프리세트되어 출력단자()로 저전위를 출력하게 되고, 또한 저전위의 제어신호(RS1)가 카운터부(20)의 카운터(21)(22)의 로드단자()에 인가되므로 카운터(21)(22)는 데이타 셀렉터(13)(14)가 출력하는 카운트값을 로드한 후 클럭신호(CLK1)를 카운트하게 되고, 이때 업/다운단자(U/D)가 전원단자(Vcc)에 접속되어 있으므로 카운터부(20)는 클럭신호(CLK1)를 다은 카운트하게 된다.Thus when the control signal (RS 1) at the input of the low potential state, the preset terminal of the flip-flop 32 of the control signal (RS 1) of the low potential horizontal synchronizing signal output section 30 ( ), The flip-flop 32 is preset to output terminal ( The low potential is outputted to the load terminal, and the low potential control signal RS 1 is applied to the load terminals of the counters 21 and 22 of the counter unit 20. ), The counters 21 and 22 load the count value output by the data selector 13 and 14, and then count the clock signal CLK 1. At this time, the up / down terminal U / D Is connected to the power supply terminal Vcc, the counter unit 20 counts the clock signal CLK 1 again .

이와 같은 상태에서 카운터부(20)의 다운카운트가 완료되어 카운터(23)의 리플클럭 출력단자()로 저전위가 출력되면, 그 저전위는 플립플롭(31)의 입력단자(D)에 입력되므로 상기 플립플롭(31)은 출력단자()로 저전위로 출력하게 되고, 그 출력한 저전위에 의해 플립플롭(32)의 출력단자()로 고전위가 출력되며, 이와같은 동작을 계속 반복수행하여 상기 플립플롭(32)이 출력단자()로 수평동기신호를 출력하게 된다.In this state, the down count of the counter unit 20 is completed and the ripple clock output terminal of the counter 23 ( When the low potential is output to the low potential is input to the input terminal (D) of the flip-flop 31, the flip-flop 31 is output terminal ( Output at low potential, and the output terminal of the flip-flop 32 by the output low potential The high potential is outputted at the same time, and the above operation is repeatedly performed so that the flip-flop 32 is output terminal ( ) Will output a horizontal sync signal.

그러나, 상기와 같은 종래의 수평동기신호 제어회로는 제어신호() 즉, 입력동기신호가 고전위로될 때부터 카운터부(20)를 동작시켜 원하는 위치에서 수평동기신호를 고전위로 만든후 일정시간 동안 그 고전위 상태를 계속 유지시키는 것으로, 수평동기신호의 상승 구간만을 제어할 수 있고, 하강 구간은 제어할 수 없어 평면 표시기의 표시화면이 불안정하고, 또한 데이타가 수평동기신호를 벗어나 있을 경우에는 복잡한 엔코팅회로(encoding circuit)가 필요하게 되는 문제점이 있었다.However, the conventional horizontal synchronous signal control circuit as described above has a control signal ( That is, the counter 20 is operated from the time when the input synchronization signal becomes high potential to make the horizontal synchronization signal high potential at a desired position, and then maintains the high potential state for a predetermined time. Only the control can be controlled, and the falling section cannot be controlled, so that the display screen of the flat panel display is unstable, and there is a problem in that a complicated encoding circuit is required when the data is out of the horizontal synchronization signal.

본 고안은 이와 같은 종래의 문제점을 감안하여, 수평동기신호의 펄스폭을 클럭신호에 동기시켜 수평동기신호의 상승과 하강위치를 제어함으로써 그래픽모드와 평판표시기를 제어하는, 제어회로를 제공함에 그 목적이 있는 것이다.SUMMARY OF THE INVENTION In view of such a conventional problem, the present invention provides a control circuit that controls the graphic mode and the flat panel display by controlling the rising and falling positions of the horizontal synchronization signal by synchronizing the pulse width of the horizontal synchronization signal with a clock signal. There is a purpose.

상기한 본 고안의 목적을 달성하기 위한 기술적 수단은 카운트 값 세팅부에 세팅된 카운트값부터 클럭신호를 다운카운트하는 카운터부의 출력신호로 수평동기신호를 발생시키는 평판 표시기용 수평 동기신호 제어회로에 있어서, 상기 카운터부가 세팅된 카운트값의 다운 카운트를 완료한 후 평판 표시기의 수평화소수 만큼 클럭신호를 다은 카운트하였는지를 검출하는 제 1의 오아게이트와, 상기 오아게이트의 출력신호 및 제어신호로 상기 카운터부가 카운트값 세팅부의 세팅 카운터값부터 다운카운트하는 것을 반복하게 하는 제 2 의 오아게이트와, 상기 클럭신호 및 제 1의 오아게이트의 출력신호로 클럭신호에 동기되는 수평동기신호를 출력하는 플립플롭으로 구성함을 특징으로 한다.Technical means for achieving the object of the present invention is a horizontal synchronizing signal control circuit for generating a horizontal synchronizing signal from the count value set in the count value setting unit to the output signal of the counter unit for down counting the clock signal; And a first oragate for detecting whether the clock signal has been counted by the horizontal pixel number of the flat panel display after the counter unit has completed the down count of the set count value, and the counter unit includes an output signal and a control signal of the oragate. A second orifice that repeats counting down from a setting counter value of the count value setting section, and a flip-flop that outputs a horizontal synchronization signal synchronized with a clock signal with the output signal of the clock signal and the first orifice; It is characterized by.

이를 첨부된 제 2 도의 도면을 참조하여 상세히 설명하면 다음과 같으며, 여기서 종래와 동일한 부위에는 동일부호를 부여하였다.This will be described in detail with reference to the accompanying drawings of FIG. 2, where the same reference numerals are given to the same parts as in the prior art.

제 2 도는 수평으로 640개의 화소를 가지는 평판표시기에 적용되는 본 고안의 수평동기신호 제어회로의 실시예도로서 이에 도시된 바와같이, 카운트값 세팅부(10)에 세팅된 카운트값부터 다운카운트하는 카운터부(20)의 출력신호로 수평동기신호를 발생하는 평판 표시기용 수평동기신호 제어회로에 있어서, 카운터부(20)의 카운터(22)의 출력단자(QD)와 카운터(23)의 출력단자(QB)를 오아게이트(OR1)를 통한후 플립플롭(40)의 입력단자(D)에 접속함과 아울러 그 접속점을 제어신호(RS1)와 함께 오아 게이트(OR2)를 통해 카운터부(20)의 카운터(21-23)의 로드단자()에 접속하고, 상기 플립플롭(40)의 클럭단자(CLK)에는 클럭신호(CLK1)가 인가되게 하여 플립플롭(40)의 출력단자(Q)로 수평동기신호(HC3)가 출력되게 구성하였다.2 is an embodiment of a horizontal synchronous signal control circuit of the present invention applied to a flat panel display having 640 pixels horizontally. As shown in FIG. 2, a counter for counting down from the count value set in the count value setting unit 10 is shown. In the horizontal synchronizing signal control circuit for a flat panel display which generates a horizontal synchronizing signal with the output signal of the unit 20, the output terminal QD of the counter 22 of the counter unit 20 and the output terminal of the counter 23 ( The QB is connected to the input terminal D of the flip-flop 40 through the ora gate OR 1 , and the connection point is connected to the input terminal D together with the control signal RS 1 through the ora gate OR 2 . Rod terminal of counter 21-23 of 20) ) And a clock signal CLK 1 is applied to the clock terminal CLK of the flip-flop 40 so that the horizontal synchronization signal HC 3 is output to the output terminal Q of the flip-flop 40. Configured.

이와같이 구성된 본 고안은 전원단자(Vcc)에 전원이 인가된 상태에서 카운트값 세팅부(10)는 스위칭부(11)(12)에 세팅되어 있는 카운트값을 선택신호(SEL)에 따라 데이타 셀렉터(13)(14)가 선택 출력하게 되고, 이 선택출력한 카운트값을 카운터부(20)가 로드한후 클럭신호(CLK1)를 다운카운트 하게 된다.According to the present invention configured as described above, in a state in which power is applied to the power supply terminal Vcc, the count value setting unit 10 selects the count value set in the switching units 11 and 12 according to the selection signal SEL. 13) 14 selects and outputs the count value, which is output by the counter unit 20, and then counts down the clock signal CLK 1 .

이와 같은 상태에서 상기 카운터부(20)의 카운터(21,22)가 다운카운트를 완료하면, 모두 저전위를 출력한 전체 출력단자(QA-QD)를 고전위로 하고 계속 다운 카운트를 수행하게 되며, 이와 같은 상태에서 640의 클럭신호(CLK1)를 다운카운터 하게 되면, 카운터(23)(22)(21)의 출력단자(QB,QA)(QD-QA)(QD-DA)로 "0101111111"을 출력하게 된다.In this state, when the counters 21 and 22 of the counter unit 20 complete the down count, all the output terminals QA-QD outputting low potentials are all set to high potentials and continue to count down. In this state, when the 640 clock signal CLK 1 is down counted, the output terminals QB and QA (QD-QA) and QD-DA of the counters 23, 22 and 21 are “0101111111”. Will print

따라서 오아게이트(OR1)기 저전위를 출력하게 되고, 오아게이트(OR2)로 저전위를 출력하여 카운터(21-23)의 로드단자()에 인가되므로 상기 카운터부(20)는 카운터값 세팅부(10)의 카운트값을 로드한 후 다운 카운터하는 동작을 반복 수행하고, 또한 상기 오아게이트(OR1)에서 출력된 저전위가 플립플롭(40)이 입력단자(D)에 인가되므로 상기 플립플롭(40)의 출력단자(Q)로 저전위를 출력한 후 상기 카운터부(20)가 카운트값 세팅부(10)의 카운트값을 로드하여 상기 오아케이트(OR1)가 고전위를 출력할 때 출력단자(Q)로 고전위를 출력 즉, 플립플롭(40)은 클럭신호(CLK1)의 펄스폭과 동일한 펄수폭을 가지는 수평동기신호(HS3)를 출력하게 된다.Therefore, the low potential is output to the oragate (OR 1 ), and the low potential is output to the oragate (OR 2 ), so that the load terminals of the counters 21 to 23 ( ), The counter unit 20 repeatedly loads the count value of the counter value setting unit 10 and then performs a down counter, and the low potential output from the oragate OR 1 is flip-flop. Since 40 is applied to the input terminal D, the counter unit 20 loads the count value of the count value setting unit 10 after outputting the low potential to the output terminal Q of the flip-flop 40. When the orient (OR 1 ) outputs a high potential, the high potential is output to the output terminal (Q), that is, the flip-flop 40 has a horizontal pulse width equal to the pulse width of the clock signal CLK 1 . Output the signal HS 3 .

한편, 상기에서는 수평으로 640개의 화소를 가지는 평탄 표시기를 예로들어 수평동기신호(HS3)를 발생시켰으나, 본 고안을 실시함에 있어서 평판표시기의 수평화소의 수에 따라 카운터부(20)의 출력단자(QA-QD)와 오아게이트(OR1)의입력단자의 접속을 변경시켜 평판 표시기의 수평화소의 수에 적합한 수평동기신호를 발생시키도록 간단히 변경실시할 수 있다.On the other hand, in the above, the horizontal synchronization signal (HS 3 ) is generated by taking a flat display having 640 pixels horizontally as an example. However, according to the present invention, the output terminal of the counter unit 20 depends on the number of horizontal pixels of the flat panel display. It is possible to simply change the connection of the input terminals of the QA-QD and the OR gate OR 1 to generate a horizontal synchronization signal suitable for the number of horizontal pixels of the flat panel display.

이상에서 상세히 설명한 바와 같이 본 고안은 클럭신호에 동기시켜 수평동기신호의 상승구간은 물론 하강구간도 제어하면서 발생 시키므로 평판 표시기의 표시화면이 흔들림이 없이 안정됨은 물론 데이타가 수평동기신호에 벗어나 있을 경우에도 적용할 수 있는 등의 효과가 있다.As described in detail above, the present invention is generated by controlling the rising and falling sections of the horizontal synchronization signal in synchronization with the clock signal, so that the display screen of the flat panel display is stable without shaking, and the data is out of the horizontal synchronization signal. It can be applied to such effects.

Claims (1)

카운트값 세팅부(10)에 세팅된 카운트값부터 클럭신호(CLK1)를 다운카운트하는 카운터부(20)의 출력신호로 수평동기신호를 발생시키는 평판표시기용 수평동기신호 제어회로에 있어서, 상기 카운터부(20)가 세팅된 카운트값의 다운 카운트를 완료한후 평판표시기의 수평화소수 만큼 클럭신호(CLK1)를 다운 카운트하였는지를 검출하는 오아게이트(OR1)와, 상기 오아게이트(OR1)의 출력신호 및 제어신호(RS1)로 상기 카운터부(20)가 카운트값 세팅부(10)의 세팅카운터값부터 다운카운트하는 것을 반복하게 하는 오아게이트(OR2)와, 상기 클럭신호(CLK1) 및 오아게이트(OR2)의 출력신호로 클럭신호(CLK1)에 동기되는 수평동기신호(HS)를 출력하는 플립플롭(40)으로 구성함을 특징으로 하는 평판표시기용 수평동기신호 제어회로.In the horizontal synchronizing signal control circuit for a flat panel display which generates a horizontal synchronizing signal from the count value set in the count value setting unit 10 to the output signal of the counter unit 20 which down counts the clock signal CLK 1 . An oragate OR 1 for detecting whether the counter 20 has down counted the clock signal CLK 1 by the horizontal pixel number of the flat panel display after completing the down count of the set count value, and the oragate OR 1. OA gate OR 2 which causes the counter unit 20 to repeat counting down from the setting counter value of the count value setting unit 10 with an output signal and a control signal RS 1 , and the clock signal ( The horizontal synchronous signal for a flat panel display comprising a flip-flop 40 which outputs a horizontal synchronous signal HS synchronized with the clock signal CLK 1 as an output signal of CLK 1 ) and OA gate OR 2 . Control circuit.
KR2019890019215U 1989-12-18 1989-12-18 Control circuit of parallel synchronizing signal for flat display KR920004991Y1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR2019890019215U KR920004991Y1 (en) 1989-12-18 1989-12-18 Control circuit of parallel synchronizing signal for flat display
JP400936U JPH0658673U (en) 1989-12-18 1990-12-18 Horizontal sync signal control circuit for flat panel display
DE4040499A DE4040499A1 (en) 1989-12-18 1990-12-18 Horizontal sync. signal control circuit for flat display panel - corrects horizontal sync. signal by using counters and analysers to detect differences in signal period

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KR2019890019215U KR920004991Y1 (en) 1989-12-18 1989-12-18 Control circuit of parallel synchronizing signal for flat display

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KR910012450U KR910012450U (en) 1991-07-30
KR920004991Y1 true KR920004991Y1 (en) 1992-07-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100412306B1 (en) * 1997-06-12 2004-03-26 삼성전자주식회사 Jammed paper removing apparatus for double sided printer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100412306B1 (en) * 1997-06-12 2004-03-26 삼성전자주식회사 Jammed paper removing apparatus for double sided printer

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DE4040499A1 (en) 1991-06-20
DE4040499C2 (en) 1992-03-19
KR910012450U (en) 1991-07-30
JPH0658673U (en) 1994-08-12

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