KR100204807B1 - A graphic control apparatus with picture in screen function - Google Patents

Abstract

The present invention relates to a graphics control apparatus for displaying desired video memory data by selecting a PIS region of a certain portion of a monitor screen, wherein the graphics control apparatus receiving coordinates of the monitor screen displays an address corresponding to a PIS region of the monitor screen Can be replaced with the PIS address output from the PIS control unit through the multiplexer. Therefore, the data preliminarily stored in the replaced video memory address can be stored in a predetermined area of the monitor screen, that is, in the PIS area, As shown in FIG.

Description

A graphic control apparatus with picture in screen function (PIS)

FIG. 1 is a view showing an operation screen of a conventional graphic control apparatus; FIG.

FIG. 2 is a block diagram schematically showing a configuration of a graphic control apparatus according to the present invention; FIG.

FIG. 3 is a display showing an operation screen of a graphic control apparatus according to an embodiment of the present invention; FIG.

FIG. 4 is a timing diagram according to an embodiment of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

10: horizontal counter section 12: PIS horizontal comparison section

14: Vertical counter part 16: PIS vertical comparison part

18: PIS control unit 20: Video memory address generator

22: Multiplexer

[Industrial Applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a graphics control apparatus, and more particularly, to a graphics control apparatus for selecting a PIS region of a monitor screen to display desired video memory data.

[Prior Art and Problems]

The microcomputer can be roughly divided into three parts. First, there is a microcomputer, a keyboard, a drive, and a monitor used as an output device. In the microcomputer main body, there is a central processing unit (CPU) to carry out various calculations and control. In general, for efficiency of use of a microcomputer, the input / output device is not directly controlled by the central processing unit, A special device is used for controlling the display device. Particularly, the part that controls the monitor output device is called a video card. If the programmer commands the computer to output characters and pictures on the monitor screen, the text processor will send the video card its code and attributes (color, etc.) Color, and so on. In case of graphic output, if you give the color code to be displayed on the screen, the video card creates the color according to the code and outputs it to the position of the desired screen.

The video card used in the microcomputer has a plurality of chips mounted on a PCB (printed circuit board), and most of the video cards are inserted into slots. Since these boards can be inserted into the slot at any time and then pulled out, the video card can use another one, even if the model of the microcomputer body is the same. The general configuration of the video card includes a graphics accelerator (VGA chip), a video memory, a bios ROM, a RAMDAC, and the like. The graphic accelerator includes a graphic controller, an attribute controller, a timing controller, and a CRT controller.

The graphic controller periodically lends data written from the central processing unit to the video memory and displays it on the monitor screen. At this time, the graphic controller sequentially lays data from address 0 of the video memory to a predetermined address of the video memory corresponding to the last coordinate of the monitor screen. FIG. 1 shows the relationship between the data displayed on the monitor screen and the address of the video memory according to the above-described method.

The data stored in address 0 of the video memory is displayed on the upper left of the monitor screen, and the data of the next video memory address is displayed on the right side of the displayed data. In this manner, the monitor screen and the video memory are sequentially mapped from address 0 of the video memory to a predetermined address indicating the end of the monitor screen, thereby displaying on the entire monitor screen.

However, according to the above-described conventional graphic control device, when the video memory data is displayed in order from the address 0 to a predetermined address indicating the end of the monitor screen in a hardware-like manner, The desired video memory data can not be displayed.

[Object of the invention]

Accordingly, it is an object of the present invention to provide a graphic control device for displaying desired data by selecting a PIS area of a certain portion of a monitor screen.

SUMMARY OF THE INVENTION [

According to an aspect of the present invention, there is provided a graphic control apparatus for selecting a PIS region of a certain portion of a monitor screen to display another screen, wherein a predetermined horizontal coordinate value of the monitor screen is A horizontal counter unit for receiving and outputting a next horizontal coordinate value; A horizontal coordinate value output from the horizontal counter unit and a PIS horizontal start point and an end point register value of the PIS region applied from the outside to define a horizontal region of the PIS region, A comparison unit; A vertical counter for receiving a predetermined vertical coordinate value of the monitor screen and outputting a next vertical coordinate value; A vertical coordinate value output from the vertical counter unit and a PIS vertical start point and an end point register value of the PIS region applied from the outside to define a vertical PIS region of the PIS region, A vertical comparison unit; A PIS control unit for receiving a PIS start address register value and an offset register value from the PIS horizontal comparison unit and the PIS vertical comparison unit, and outputting a PIS selection signal and a PIS address defining the PIS area; A video memory address generator for generating an address of data to be displayed on the monitor screen except for the PIS area; And a multiplexer for receiving an address output from the video memory address generator and each signal output from the PIS controller to output a corresponding video memory address.

In a preferred embodiment of the apparatus, the PIS vertical start and end point register values have a value less than or equal to a value within a resolution range of the monitor screen.

In a preferred embodiment of the present invention, the PIS control unit receives the PIS vertical start and end point signals, the PIS horizontal start and end point signals, and internally generates a PIS horizontal enable signal and a PIS vertical enable signal do.

In a preferred embodiment of the present invention, the PIS control unit outputs the PIS selection signal using the PIS horizontal enable signal and the PIS vertical enable signal.

In a preferred embodiment of the present invention, the multiplexer outputs the PIS address in a section in which the PIS selection signal is enabled.

In a preferred embodiment of the present invention, the multiplexer outputs the pls address in a section in which the PIS selection signal is enabled.

According to a preferred embodiment of the present invention, the multiplexer outputs the address output from the video memory address generator in a period during which the pls selection signal is disabled.

[Action]

By this method, the PIS area of a certain portion of the monitor screen can be selected and the desired video memory data can be displayed in the selected area of the selected area.

[Example]

Reference will now be made in detail to the preferred embodiments of the present invention with reference to the accompanying drawings.

Referring to FIG. 2, a graphics control apparatus having a new PIS function of the present invention includes a PIS vertical start and end point register value (for example, PIS_VSR and PIS_VER) and the PIS horizontal start and end point register values (PIS_HSR and PIS_HER) are externally applied to the PIS vertical comparison section 12 and the PIS horizontal comparison section 16, respectively. (PIS_HS, PIS_HE, PIS_VS) by comparing predetermined vertical and horizontal coordinate values (vertical count and horizontal count) of the monitor screen with a plurality of register values (PIS_VSR, PIS_VER, PIS_HSR, PIS_HER) (PIS_SS) and a PIS address (PIS address) for defining the PIS region are output through the PIS control unit 18 receiving the input PIS_RE and the PIS_VE.

The multiplexer 22 receiving the PIS address and the address (IVMA) of the data to be displayed on the monitor screen except for the PIS region receives the PIS address signal in the period in which the PIS selection signal PIS_SS is enabled (IVMA) of the data corresponding to the monitor screen except for the PIS area is output in a period in which the PIS address and the PIS_SS signal are disabled.

According to this apparatus, the graphic control apparatus receiving the coordinates of the monitor screen receives the address (IVMA) corresponding to the PIS region of the monitor screen through the multiplexer 22, the PIS address (PIS address) output from the PIS control unit 18, . Therefore, it is possible to display the desired video memory data in a hardware-like manner in the area of a certain portion of the monitor screen, that is, the PIS area, with the data read from the replaced video memory address.

FIG. 2 is a block diagram schematically showing a configuration of a graphic control apparatus according to the present invention.

Referring to FIG. 2, in the graphic control device for selecting another PIS area of a certain portion of the monitor screen, the horizontal counter 10 receives a predetermined horizontal coordinate value of the monitor screen, The PIS horizontal comparator 12 compares the horizontal coordinate value output from the horizontal counter 10 and the PIS horizontal start value of the PIS area applied from the outside in order to define a horizontal area of the PIS area. And the end point register values PIS_HSR and PIS_HER, and outputs the PIS horizontal start and end point signals PIS_HS and PIS_HE.

The vertical counter 14 receives a predetermined vertical coordinate value of the monitor screen and outputs a next vertical coordinate value. The PIS vertical comparator 16 compares the vertical (PIS_VSR, PIS_VER) from the vertical coordinate value output from the counter unit 14 and the PIS vertical start and end point register values (PIS_VSR and PIS_VER) of the PIS region applied from the outside, and outputs the PIS vertical start and end point signals PIS_VS and PIS_VE .

Next, the PIS control unit 18 receives the signals PIS_HS, PIS_HE, PIS_VS, and PIS_VE output from the PIS horizontal comparison unit 12 and the PIS vertical comparison unit 16, the PIS start address register value PIS_SAR, And outputs a PIS selection signal (PIS_SS) and a PIS address (PIS address), which define the PIS region, by receiving the offset register value (OR). The video memory address generator 20 generates an address (IVMA) of data to be displayed on the monitor screen except for the PIS area. The multiplexer 22 receives the address IVMA output from the video memory address generator 20 and the signals PIS address and PIS_SS output from the PIS controller 18 to output a corresponding video memory address do.

Here, the PIS vertical start and end point register values (PIS_VSR, PIS_VER) are set to have a value less than or equal to a value within the resolution range of the monitor screen. The PIS control unit 18 receives the PIS vertical start and end point signals PIS_VS and PIS_VE and the PIS horizontal start and end point signals PIS_HS and PIS_HE to internally generate a PIS horizontal enable signal Generates a PIS vertical enable signal and outputs the PIS selection signal PIS_SS using the PIS horizontal enable signal and the PIS vertical enable signal. do. The multiplexer 22 selects the PIS address in a period in which the PIS selection signal PIS_SS is enabled and the PIS selection signal PIS_SS in a period in which the PIS selection signal PIS_SS is disabled And outputs the address (IVMA) output from the video memory address generator 20.

The graphic control apparatus shown in FIG. 2 selects a certain area to be displayed on the monitor screen, that is, a PIS area, and outputs an address (IVMA) corresponding to a predetermined coordinate value of the monitor screen from the PIS control unit 18 And the data indicated by the replaced video memory address is displayed in the PIS area of the monitor screen by replacing the PIS address with the PIS address.

In other words, by implementing two video memory address generating circuits internally in the graphics control device, the graphics control device can selectively send any one of the addresses output from the two video memory address generating circuits to the video memory It is possible to display the video memory data to be displayed in the PIS area of a certain portion of the monitor screen. The graphic control apparatus as shown in FIG. 2 operates as follows.

First, the vertical counter 14 receives a predetermined vertical coordinate value of the monitor screen and outputs a next vertical coordinate value. The PIS vertical comparison unit 16 receives the PIS vertical start and end point register values (PIS_VSR and PIS_VER) of the PIS region to be displayed in the PIS region and the vertical coordinate values output from the vertical counter unit 14 (PIS_VER, PIS_VSR) and the vertical coordinate value. Thus, the PIS vertical comparison unit 16 outputs the PIS vertical start and end point signals PIS_VS and PIS_VE indicating the start and end of the PIS region from the vertical line of the vertical coordinate on the monitor screen, The vertical region of the PIS region is determined.

Here, the PIS vertical start and end point register values (PIS_VSR and PIS_VER) are set only when a value within a resolution range corresponding to the monitor screen is designated. If the PIS vertical start and end point register values (PIS_VSR, PIS_VER) have a value larger than the resolution corresponding to the monitor screen, the PIS area is not selected and only the existing screen is displayed. In other words, when it is desired not to select the PIS area, the values (PIS_VSR, PIS_VER) of the PIS registers may be set to a value larger than the resolution corresponding to the monitor screen.

Next, the horizontal counter unit 10 receives a predetermined principal-point coordinate value of the monitor screen and outputs a next horizontal coordinate value. The PIS horizontal comparison unit 12 receives the PIS horizontal start and end point register values (PIS_HSR and PIS_HER) of the PIS region to be displayed in the PIS region and the horizontal coordinate values output from the horizontal counter unit 10 The two register values (PIS_HSR, PIS_HER) and the horizontal coordinate value are compared. The PIS horizontal comparison unit 12 outputs the PIS horizontal start and end point signals PIS_HS and PIS_HE indicating the start and end of the PIS region from the second row of the horizontal coordinates on the monitor screen, The horizontal region of the PIS region is determined. Here, the horizontal and vertical regions of the scrambling PIS region are defined not simultaneously but sequentially.

The PIS control unit 18 receives the signals PIS_HS, PIS_HE, PIS_VS and PIS_VE output from the PIS vertical and horizontal comparison units 12 and 16, the PIS start address register value PIS_SAR and the offset register value OR). 3, the PIS control unit 18 internally generates a PIS horizontal enable signal (PIS_H, PIS_HE) by the PIS horizontal start and end point signals PIS_HS and PIS_HE output from the PIS horizontal comparison unit 12, (PIS horizontal enable). The PIS vertical enable signal PIS vertical enable signal is generated by the PIS vertical start and end point signals PIS_VS and PIS_VE outputted from the PIS vertical comparison unit 16. Next, the PIS control unit 18 generates a PIS selection signal (PIS_SS) defining the PIS region using the PIS horizontal enable signal (PIS horizontal enable signal) and the PIS vertical enable signal (PIS vertical enable signal) And outputs an address (PIS address).

The address IVMA output from the video memory address generator 20 for generating the address IVMA of the data to be displayed on the monitor screen except for the PIS area and the signals IVMA output from the PIS control unit 18 The multiplexer 22 receiving the PIS address and PIS_SS outputs the PIS address in a period in which the PIS selection signal PIS_SS is enabled as shown in the timing chart of FIG. . As shown in FIG. 4, by outputting the address (IVMA) output from the video memory address generator 20 in the section during which the data is disabled, desired data is stored in the PIS area of a certain portion of the monitor screen It can be displayed in a hardware-like manner.

[Effects of the Invention]

As described above, the graphics control apparatus receiving the coordinates of the monitor screen can replace the address corresponding to the PIS region of the monitor screen with the PIS address output from the PIS control unit through the multiplexer. Therefore, it is possible to display the desired video memory data in a hardware-like manner in the area of a certain portion of the monitor screen, that is, the PIS area, with the data read from the replaced video memory address.

Claims (6)

A graphic control device for displaying a different screen by selecting a PIS area of a certain portion of a monitor screen, comprising: a horizontal counter (10) for receiving a predetermined horizontal coordinate value of the monitor screen and outputting a next horizontal coordinate value; The horizontal coordinate value output from the horizontal counter 10 and the PIS horizontal start and end point register values (PIS_HSR, PIS_HER) of the PIS region applied from the outside are input to define a horizontal region of the PIS region, And a PIS horizontal comparator 12 for outputting the end point signals PIS_HS and PIS_HE; A vertical counter (14) for receiving a predetermined vertical coordinate value of the monitor screen and outputting a next vertical coordinate value; Vertical coordinate values output from the vertical counter unit 14 and PIS vertical start and end point register values (PIS_VSR, PIS_VER) of the PIS region applied from the outside are inputted to define a PIS vertical region of the PIS region, A PIS vertical comparator 16 for outputting start and end point signals PIS_VS and PIS_VE; (PIS_HS, PIS_VS, PIS_VE), the PIS start address register value (PIS_SAR), and the register value (OR) output from the PIS horizontal comparator 12 and the PIS vertical comparator 16, A PIS control unit 18 for outputting a PIS selection signal (PIS_SS) defining a PIS region and a PIS address (PIS address); A video memory address generator 20 for generating an address (IVMA) of data to be displayed on the monitor screen except for the PIS area; A multiplexer 22 for receiving an address IVMA output from the video memory address generator 20 and a PIS address and a PIS_SS output from the PIS controller 18 to output a corresponding video memory address, Wherein the graphics control device comprises: The graphics control apparatus according to claim 1, wherein the PIS vertical start and end point register values (PIS_VSR, PIS_VER) have a value less than or equal to a value within a resolution range of the monitor screen. The PIS control apparatus according to claim 1, wherein the PIS control unit (18) receives the PIS vertical start and end point signals (PIS_VS, PIS_VE), PIS horizontal start and end point signals (PIS_HS, PIS_HE) horizontal enable) and a PIS vertical enable signal (PIS vertical enable). 4. The method of claim 3, wherein the PIS control unit (18) outputs the PIS selection signal (PIS_SS) using the PIS horizontal enable signal (PIS horizontal enable signal) and the PIS vertical enable signal Characterized by a graphic control device. The graphics control apparatus according to claim 1, wherein the multiplexer (22) outputs the PIS address in a period in which the PIS selection signal (PIS_SS) is enabled. The video decoder according to claim 5, wherein the multiplexer (22) outputs the address (IVMA) output from the video memory address generator (20) in a period during which the PIS selection signal (PIS_SS) Graphics control device.