KR910016164A - Scrambling system - Google Patents

Scrambling system Download PDF

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Publication number
KR910016164A
KR910016164A KR1019900002567A KR900002567A KR910016164A KR 910016164 A KR910016164 A KR 910016164A KR 1019900002567 A KR1019900002567 A KR 1019900002567A KR 900002567 A KR900002567 A KR 900002567A KR 910016164 A KR910016164 A KR 910016164A
Authority
KR
South Korea
Prior art keywords
signal
address
output
load
outputting
Prior art date
Application number
KR1019900002567A
Other languages
Korean (ko)
Other versions
KR920009184B1 (en
Inventor
강경진
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019900002567A priority Critical patent/KR920009184B1/en
Publication of KR910016164A publication Critical patent/KR910016164A/en
Application granted granted Critical
Publication of KR920009184B1 publication Critical patent/KR920009184B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/16—Analogue secrecy systems; Analogue subscription systems
    • H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

내용 없음No content

Description

스크램블링 시스템Scrambling system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 스크램블링 시스템의 블록도, 제4도의 (가) 내지 (사)는 제3도 각부의 파형도.3 is a block diagram of the scrambling system of the present invention, (a) to (g) of FIG.

Claims (1)

A/D변환기(1)를 통해 입력되는 복합영상신호(Vin)의 디지탈데이타를 라이트어드레스카운터(4)의 출력 어드레스에 따라 번갈아가며 저장하는 라인메모리(2a, 2b)와, 리드어드레스카운터(5)의 출력어드레스에 따라 상기 라인메모리(2a, 2b)에서 리드된 디지탈 데이타를 아날로그의 신호로 출력하는 스크램블링 시스템에 있어서, 상기 리드어드레스카운터(5)에 불규칙번호를 제공하는 불규칙번호 발생기(21)와, 상기 복합영상신호(Vin)에서 이전 수평주사선의 프론트 포오치 구간과 현재 수평주사선의 백 포오치 구간을 모두 포함하는 수평귀선 구간을 검출하는 수평귀선 구간 검출기(22)와, 상기 수평귀선구간검출기(22) 출력신호의 하강에지부에서 상기 라이트 및 리드어드레스카운터(4, 5)의 클리어 신호를 출력하는 클리어신호발생기(23)와, 상기 수평귀선구간 검출기(22) 출력신호의 상승에지부에서 로드신호를 발생하는 로드신호 발생기(24)와,상기 리드어드레스카운터(5)의 출력어드레스를 라인로테이션값과 비교하여 같아지는 순간 로드신호를 출력하는 비교기(25)와, 상기 로드신호 발생기(24) 및 비교기(25)의 로드신호를 논리적하여 상기 리드어드레스카운터(5)에 어드레스 변환신호로 제공하는 앤드게이트(AD1)로 구성된 것을 특징으로 하는 스크램블링 시스템.Line memories 2a and 2b which alternately store digital data of the composite video signal Vin input through the A / D converter 1 according to the output address of the write address counter 4 and the read address counter 5 In the scrambling system for outputting the digital data read from the line memories (2a, 2b) as an analog signal according to the output address of), an irregular number generator (21) for providing an irregular number to the lead address counter (5). And a horizontal retrace section detector 22 for detecting a horizontal retrace section including both a front porch section of a previous horizontal scan line and a back porch section of a current horizontal scan line in the composite image signal Vin. A clear signal generator 23 for outputting a clear signal of the write and read address counters 4 and 5 at the falling edge of the detector 22 output signal and the horizontal retrace section test; A load signal generator 24 generating a load signal at a rising edge of the output signal of the output signal 22 and a comparator for outputting a load signal at the same time by comparing the output address of the lead address counter 5 with a line rotation value. And an AND gate AD1 which logically provides the load signals of the load signal generator 24 and the comparator 25 as an address conversion signal to the lead addresser 5. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900002567A 1990-02-27 1990-02-27 Scrambling system KR920009184B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002567A KR920009184B1 (en) 1990-02-27 1990-02-27 Scrambling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002567A KR920009184B1 (en) 1990-02-27 1990-02-27 Scrambling system

Publications (2)

Publication Number Publication Date
KR910016164A true KR910016164A (en) 1991-09-30
KR920009184B1 KR920009184B1 (en) 1992-10-14

Family

ID=19296508

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002567A KR920009184B1 (en) 1990-02-27 1990-02-27 Scrambling system

Country Status (1)

Country Link
KR (1) KR920009184B1 (en)

Also Published As

Publication number Publication date
KR920009184B1 (en) 1992-10-14

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