KR920009184B1 - Scrambling system - Google Patents

Abstract

A scrambling system produces two load signals during one horizontal period, and achieves the result that obtains three address transitions by two address transitions. The system comprises two line memories (2a,2b) for alternately storing the digital data of the composite video signal (Vin) according to the write address counter (4), an irregular address generater (21) for providing the irregular address to a read address counter (5), a horizontal feedback interval detector (22) for detecting the horizontal feedback interval including the front porch interval of the previous horizontal scanning line and the back porch interval of the present horizontal scanning line, a clear signal generater (23) for providing the clear signal to the write and read address counters (4,5), a load signal generater (24), a comparator (25) for comparing the output address of a read address counter (5) with the line rotation value, and an AND gate (AD1).

Description

Scrambling system

1 is a block diagram of a general scrambling system.

2A and 2B are waveform diagrams of respective parts of FIG.

2c is a waveform diagram of a clear signal.

2d is a waveform diagram of a load signal.

3 is a block diagram of a scrambling system of the present invention.

4A to 4G are waveform diagrams of respective parts of FIG. 3.

* Explanation of symbols for the main parts of the drawings

1: A / D Converter 2a, 2b: Line Memory

3: D / A Converter 4: Lead Address Counter

5: light address counter 6: multiplexer

21: irregular number generator 22: horizontal retrace section detector

23: clear signal generator 25: load signal generator

25: comparator AD1: endgate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scrambling system, and more particularly, to a scrambling system in which a scan section of one horizontal scan line is changed, divided into three sections, and then scrambling is divided into four sections to obtain a result of scrambling will be.

FIG. 1 is a block diagram of a general scrambling system for scrambling a horizontal scan line by dividing the scanning section into four sections. As shown therein, analog (A) / digital converting an analog composite video signal (Vin) into digital data. (D) Converter 1, line memories 2a and 2b for storing data input from said A / D converter 1, and digital data read from said line memories 2a and 2b as analog signals. D / A converter 3 for converting and outputting, a write addresser 4 for outputting an address for writing the output signal of the A / D converter 1 to line memories 2a and 2b, and an address for reading A read address counter 5, a sync separator 7 for separating the horizontal sync signal Hsyn from the composite video signal Vin, and a horizontal sync signal Hsyn separated from the sync separator 7 The light address Selection of the clear signal generator 8 provided as the load address signal of the counter 4 and the lead addresser 5, the irregular number generator 9 generating the irregular number, and the output signal of the synchronous separator 7 A multiplexer 10 for providing a clear signal to the load address of the lead addresser 5 after inputting the signal from the irregular number generator 9, and an output value of the lead addresser 5 It is composed of a load signal generator 11 which outputs a load signal so that the lead addresser 5 deforms the counter value when it matches the rotation value.

There are two methods of converting the scanning section of the horizontal scanning line by the routing, and the method of converting the scanning line of the horizontal scanning line at the time of reading and the method of converting the writing line at the time of reading, all of which have the same effect. Is as follows.

The analog composite normal signal Vin as shown in FIG. 2A is converted into digital data through the A / D converter 1, and then alternated to the line memories 2a and 2b in accordance with an address input from the write address counter 4. The stored data is read out according to the read address inputted from the read address counter 5 and then output to the analog composite video signal Vout as shown in FIG. 2B through the D / A converter 3. Hereinafter, a process of writing and reading corresponding data in the line memories 2a and 2b will be described.

As the composite video signal Vin is separated through the sync separator 7, the horizontal sync signal Hsyn is separated and provided as a selection signal to the multiplexers 6 and 10, and the clear signal generator 8 is used to clear as shown in FIG. 2C. It is output as a signal. As a result, the light address counter 4 and the lead address counter 5 are cleared to address øø, and then the light address counter 4 is located at address øø ＂where the horizontal synchronization of the composite video signal Vin starts. Although the address is output in the normal order from the above, the lead address counter 5 is normally counted up to the horizontal retrace section (T1 in FIG. 2a), and is then loaded by the load signal as shown in FIG. 2d by the load signal generator 11. The output address is converted.

That is, the count value of the read address counter 5 is converted from the end point of the first section T1 to the start point of the third section T3 by the first load signal as shown in FIGS. The corresponding data is read in (2a) or line memory (2b), and the counter value of the read address counter (5) is changed to the second section (T2) at the end of the third section (T3) by the second load signal. The data is converted into the starting point of and the corresponding data is read on the line memory 2a or the line memory 2b, and then, from the end point of the second section T2 to the starting point of the fourth section T4 by the third load signal. The data is converted and read on the line memory 2a or the line memory 2b.

When reading in this order, the composite video signal as shown in FIG. 2a is converted to the composite video signal as shown in FIG. 2b, and then converted into analog composite video signal Vout through the D / A converter 3, and each load is instantaneous. Regarding the load address required for, the number data generated by the random number generator 7 is supplied to the lead addresser 5 through the multiplex 10.

However, in this general scrambling system, three load signals must be generated during one horizontal period. Therefore, the hardware configuration is complicated, which leads to an increase in cost, and a boundary line appears in the video signal at the deformation part of the address. In the general system, since the address is changed three times, there is a problem that the image quality is reduced.

In order to solve this problem, the present invention has been made of a scrambling system which generates two load signals during one horizontal period and obtains the same result as three address transformations with two address transformations. It demonstrates in detail by drawing.

3 is a block diagram of the scrambling system of the present invention, as shown therein, an analog (A) / digital (D) converter 1 for converting an analog composite video signal Vin into digital data, and the A / D A line memory (2a, 2b) for storing data input from the converter (1), a D / A converter (3) for converting and outputting data read from the line memory (2a, 2b) into an analog signal, and a multiplexer On the write addresser 5 and its line memories 2a and 2b which provide write addresses for writing the output data of the A / D converter 1 into the line memories 2a and 2b via (6). A scrambling system composed of a lead addresser (5) for outputting an address for reading recorded data, comprising: an irregular number generator (21) for providing an irregular number to the lead addresser (5), and the composite video signal ( Horizontal ears from Vin A horizontal retrace section detector 22 that detects a section and outputs a signal according to the detection result; and at the falling edge of the pulse inputted from the horizontal retrace section detector 22, to the light address counter 4 and the lead address counter 5; A clear signal generator 23 for providing a clear signal, a load signal generator 24 for outputting a load signal at a rising edge of a pulse input from the horizontal retrace section detector 22, and the read addresser 5; A comparator 25 for outputting a load signal at the same time by comparing an output address with a line rotation value, and the load signals of the load signal generator 24 and the comparator 25 are logically finalized in the lead address counter 5. The operation and effect of the present invention constituted by the AND gate AD1 for generating the load signal of D is detailed with reference to FIG. If the description follows.

The analog composite video signal Vin is digitally converted and then alternately read to the line memories 2a and 2b according to the address of the write address counter 4, and the horizontal retrace section detector 22 is connected to the composite video signal ( Vin) and outputs a waveform as shown in FIG. 4C including both the front porch section of the previous horizontal scan line and the back porch section of the current horizontal scan line, and the horizontal retrace section detector 22. Can be easily configured using a monostable multivibrator or counter.

On the other hand, the clear signal generator 23 generates a clear signal at the falling edge portion of the signal input from the horizontal retrace section detector 22 as shown in FIG. 4D, which is a light address counter 4 and a lead address counter ( 5) to clear them. The write address counter 4 outputs the addresses in the normal order from the position where the horizontal synchronization of the composite video signal Vin is cleared after the address is cleared to the address?, But the read address counter 5 is an irregular number. The signal input from the generator 21 is counted and outputted to the write addresses of the line memories 2a and 2b, and then the address is transformed and output whenever the load signal is input from the AND gate AD1. .

Hereinafter, referring to the waveform in which the load signal is applied to the read address counter 5, the load signal generator 24 is loaded at the rising edge of the signal input from the horizontal retrace section detector 22 as shown in FIG. 4E. A signal is output to be applied to one input terminal of the AND gate AD1, and the comparator 25 compares the address value output to the lead addresser 5 with the line rotation value (P point in FIG. 4B). At the moment, the load signal is output as shown in FIG. 4f, and is applied to the other input terminal of the AND gate AD1. Accordingly, the AND gate AD1 combines load signals input to both input terminals and outputs a load signal as shown in FIG. 4G to its output terminal.

Accordingly, the lead address counter 5 corresponds to the third section T3 by the first load signal inputted at the end of the horizontal retrace section and the first section T1, as shown in FIGS. 4A and 4B. While outputting an address, an address corresponding to the second section T2 is output by the second load signal inputted at the end of the third section T3, and a horizontal period at the end of the second section T2. The output of the lead address corresponding to is completed.

As a result, the composite image signal Vin as shown in FIG. 4a is eventually read onto the line memories 2a and 2b and then scrambled as shown in FIG. 4b through the D / A converter 3 to the composite video signal Vout as shown in FIG. Is output.

As described in detail above, the present invention does not require a multiplexer for controlling the output of the random number generator, and the load signal generator is replaced with a simple comparator, thereby simplifying the configuration of the system, thereby reducing the cost. Even if the scanning interval of is divided into 4 sections and 4 sections, the same result as obtained by dividing into 4 sections is obtained, and thus the image quality can be improved.

Claims (1)

Line memories 2a and 2b which alternately store digital data of the composite video signal Vin input through the A / D converter 1 according to the output address of the write address counter 4 and the read address counter 5 In the scrambling system for outputting the digital data read from the line memories (2a, 2b) as an analog signal according to the output address of < RTI ID = 0.0 >), < / RTI > an irregular number generator 21 for providing an irregular number to the lead addresser 5 And a horizontal retrace section detector 22 for detecting a horizontal retrace section including both a front porch section of a previous horizontal scan line and a back porch section of a current horizontal scan line in the composite image signal Vin. A clear signal generator 23 for outputting clear signals of the write and read address counters 4 and 5 at the falling edge of the detector 22 output signal, and the horizontal retrace section inspection; 22. A load signal generator 24 generating a load signal at the rising edge of the output signal and a comparator for outputting a load signal at the same time by comparing the output address of the lead address counter 5 with a line rotation value. And an AND gate AD1 which logically provides the load signals of the load signal generator 24 and the comparator 25 as an address conversion signal to the lead addresser 5. .

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