KR0152765B1 - Scrambling system - Google Patents

Abstract

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Description

Image reading / writing conversion method and apparatus of scrambling system

1 is a block diagram of a conventional address generator.

FIG. 2 is a signal waveform diagram of a process of rescrambled in FIG.

3 is a signal waveform diagram of each part of FIG.

4 is a block diagram of a video signal read / write converting apparatus according to the present invention.

5 is a signal waveform diagram of a process of descrambling by rewriting as shown in FIG.

6 is a signal waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

31: random noise generator 32: second multiplexer

33: first address counter 34: second address counter

35,36: first and second line memory sections 38,48: first and second comparator sections

The present invention relates to a scrambling system of an image signal, and more particularly, to an image read / write conversion of a scrambling system which halves the number of counters of an address generator and prevents deterioration of image quality when a load signal is separately generated and descrambled. A method and apparatus are disclosed.

Conventionally, in the scrambling and descrambling, an analog / digital converted digital video signal is recorded in a line memory and read out in an arbitrary order, which can be divided into two types according to a method of recording / reading a memory.

The first is rewrite / read, and the second is rewrite / read.

The former is to scramble or descramble the video signals by writing the video signals in order from address 0 of the memory and then reading them in an arbitrary order.

In the latter rewriting, the immediately reading means that the video signal is written to a random place when writing to the memory, and when read, the scrambling or descrambling is performed by sequentially reading from address 0.

In this case, since the two methods can be selected when scrambling and one of the two methods can be selected when descrambling, a total of four methods can be used as the scrambling method.

Here, a description will be given of how to descramble on the receiving side by using the read / write function on the sending side as a scrambling and the rewriting / reading on the receiving side as an example.

FIG. 1 is a block diagram of a conventional address generator. As shown therein, a random noise generator 1 and a random noise generator 1 for generating a P value by removing noise from an input horizontal sync signal Hsync are shown in FIG. The first multiplexer section 2 selects the P value generated at < RTI ID = 0.0 > 0, < / RTI > 3) (4), first and second line memory sections (5) and (6) for receiving and outputting the first and second address counter sections (3) and (4) to write / read data; A second multiplexer section 7 for selecting a counter value of the first and second address counter sections 3 and 4, an output signal selected from the second multiplexer section 7, an address A, B and random The output value P of the noise generator 1 is compared and the selection signal is provided to the first multiplexer 2 according to the result value, and the load signal LD is generated. The comparator unit 8 receives the horizontal synchronization signal Hsync through the second inverter 12, provides a selection signal to the second multiplexer unit 7, and reads it into the second line memory unit 6. A flip-flop 10 for providing a write / write signal, a first inverter 11 for providing a read / write signal to the first line memory unit 5 by inverting an output signal of the flip-flop 10, and A first or gate 13 for providing a load signal to the first address counter unit 3 by logically combining the output signal of the first inverter 11 and the load signal LD of the comparator unit 8, and the flip A second or gate 14 for providing a load signal to the second address counter unit 4 by logically combining the output signal of the flop 10 and the load signal LD of the comparator unit 8, and the input horizontal synchronizing unit; The clock generator 9 is provided to counter the signal Hsync and provide a sampling clock to the first and second address counters 3 and 4.

A conventional address generator configured as described above will be described with reference to FIG.

First, the horizontal synchronization signal Hsync as shown in FIG. 3A is inverted through the second inverter 12 and input to the flip-flop 10.

When the inverted horizontal synchronization signal is input from the second inverter 12, the flip-flop 10 generates a selection signal and a read / write signal as shown in (b) of FIG. 3 to generate the second multiplexer 7 and the second. Input to the line memory section 6 is made.

The read / write signal as shown in (b) of FIG. 3 output from the flip-flop 10 is inverted as shown in (c) of FIG. 3 through the first inverter 11 to be formed of the first line memory unit 5 and the first line. 1 is input to the oragate 13.

On the other hand, when the first and second address counters 3 and 4 start the counter due to the first horizontal sync signal Hsync, the first multiplexer 2 selects 0 and the first and second addresses are selected. It is sent to the counter part 3 (4). At this time, no load signal is required.

In this way, when the first and second address counters 3 and 4 count up to point A in FIG. 2C, a signal as shown in FIG. 3D is generated, and the first multiplexer 2 is The P value of the random noise generator 1 is selected.

The first address counter 3 then starts counting from the P value.

At this time, since the load signal does not enter as shown in (e) of FIG. 3, the second address counter 4 continues to count up.

That is, since the second line memory section 6 is in the read mode (reading immediately) by the flip-flop 10, the second address counter section 4 is up counted.

When the value counted by the first and second address counter units 3 and 4 at P value in FIG. 2C reaches point B, a B signal is generated as shown in FIG. The first multiplexer section 2 selects the value A, and the first address counter section 3 starts counting from the value A again.

Then, when the first address counter section 3 reaches the P value, the P signal of (d) in FIG. 3 is generated, and the first multiplexer section 2 selects the B value and provides it to the first address counter section 3. Done.

Therefore, the first address counter section 3 starts counting from the B value selected by the first multiplexer section 2 and counts to the end of one horizontal scan line.

In this way, since the value recorded in the first line memory section 5 is in the read mode for the next horizontal section, the read-read signal is always high. Therefore, when data is read in order, the original signal is reproduced as shown in (e) of FIG. .

At this time, the second line memory section 6 enters the recording mode and is rewritten as described above.

The load signal LD of the first inverter 11 and the comparator unit 8 for inverting the output signal of the flip-flop 10 is compared with the output signals of the first inverter 11 and the flip-flop 10. The first and second OA gates 13 and 14 to be combined are logic gates for making signals as shown in (d) and (f) of FIG.

에 하이신호를 입력시킨면 제1어드레스 카운터부(3)의 출력신호가 선택된다.In addition, in FIG. 3B, which is the selection signal for driving the second multiplexer unit 7, the address of the line memory to be written must be selected. Since (5) is being recorded, the selection terminal of the second multiplexer section 7

When the high signal is input to the output signal of the first address counter section 3, the output signal is selected.

In (c) of FIG. 2, for example, when a horizontal line is sampled 1296 times (0-1295), the point A is 240 and the point B is 1264.

(B) of FIG. 2 is a form in which (a) rewrites the scrambled video signal. As shown in (a) of FIG. 2, sections 1, 2, 3, and 4 are replaced with sections 1, 3, 2, and 4. (D) of FIG. 2 is a read-out which reads data and addresses of the first and second line memory sections 5 and 6 of (c) as it is, and the descrambled video signal is shown in (e) of FIG. Appears on

FIG. 3B shows a read / write signal section of the second line memory section 6, and FIG. 3C shows a read / write signal section of the first line memory section 5. In FIG.

Therefore, it is theoretically simple to separate a signal such as (d) of FIG. 3 as shown in (e) and (f) of FIG. 3, but substantially with the signal of (b) and (c) of FIG. It's very hard because of motivation problems.

That is, (b) and (f), (c) and (e) in FIG. 3 do not have edges in common with each other.

This is directly related to the image quality even if the position is slightly wrong, so timing adjustment becomes important.

Accordingly, an object of the present invention, in view of such a conventional problem, the scrambling to generate a load signal, which is the most important part of the address counter unit separately and to synchronize each load signal to the horizontal synchronization to prevent deterioration of image quality during descrambling An image read / write conversion method and apparatus for a system are provided.

As a method for achieving the object of the present invention as described above, the P value obtained by the random noise generating means and the address A + B added by the adder are subtracted from the P value by the subtractor (A + BP). A value is provided to the first and second multiplexer sections, respectively, the output of the first and second multiplexer sections is data of the first and second address counter sections, and the output of the first address counter section is an address of the first line memory section. Read immediately after rewriting as input, read the second address counter section as the address input of the second line memory section, read after write directly, and output the first address counter section as the input of the first comparator section. To obtain the load signal of the first address counter section therefrom, and output the second address counter section as the input of the second comparator section therefrom, The load signal is obtained, and the horizontal synchronous signal passing through the second inverter and the flip-flop is an enable signal of the first and second comparator units, or the read / write signal of the second line memory unit or the first inverter via the first inverter. It is achieved by being used as a read / write signal. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a video signal read / write converting apparatus according to the present invention. As shown in FIG. 4, a random noise generator 31 which removes noise from an input horizontal sync signal Hsync and generates a P value, An adder 46 that adds and outputs an input address A and B, an A + B value added from the adder 46 and a P value generated from the random noise generator 31, and then subtracts an A + BP value. Selects one of the subtractor 47 and the A + BP value input from the subtractor 47 and the A, B, 0 values input from the outside by an external selection signal S1 (S2). One of the first multiplexer section 45 to output and the P value generated by the random noise generator 31 and the A, B, and 0 values input from the outside are selected by an external selection signal S1 (S2). The second multiplexer unit 32 to select, the clock signal of the clock generator 39 which receives the horizontal synchronization signal Hsync, and the external load signal The first multiplexer unit 33 counts the output selected by the second multiplexer unit 32 as data, and the first multiplexer unit by the clock signal of the clock generator 39 and an external load signal. A second address counter 34 for countering the output selected in 45 as data and the horizontal sync signal Hsync are inverted through the second inverter 42 and chip-enabled according to the inverted horizontal sync signal. The output signal of the flip-flop 40 generating the signal compares the P value of the random noise generator 31 with the output value of the second address counter 33 and the input A and B values and accordingly the second value. A first comparator 38 for outputting a selection signal S1 (S2) to the multiplexer unit 32 and a load signal to the first address counter unit 33; and a chip of the flip-flop 40; P value and the second address of the random noise generator 31 according to the enable signal The output value of the counter unit 34 is compared with the input A and B values, and accordingly, the selection signals S1 and S2 are output to the first multiplexer unit 45 and the load signal is supplied to the second address counter unit 34. A second comparator unit 48 for outputting, a first inverter 41 for inverting the output signal of the flip-flop 40 and outputting it as a read / write signal, and a read / write of the first inverter 41 First and second line memory sections 35 and 36 that read / write data counted by the first and second address counter sections 33 and 34 in accordance with the clock signal of the signal and clock generator 39. It consists of.

The operation and effects of the present invention configured as described above will be described in detail with reference to FIGS. 4 to 6.

First, the P value and the input address (A) (B) from the random noise generator 31 become the A + BP value through the adder 46 and the subtractor 47, and this value and 0, A, B One of the values is selected by the first multiplexer section 45.

In addition, the P value generated by the random noise generator 31 enters the second multiplexer 32, and selects the signal S1 (S2) from the first comparator 38 together with 0, A, and B values. ) Is selected.

In addition, the value coming from the second multiplexer section 32 is inputted to the first address counter section 33 and counted by the load signal from the first comparator section 38, and then this output is output to the first line memory section 35. To the address terminal.

On the other hand, the input of the first comparator unit 38 is composed of a signal selected from the first multiplexer unit 45 and an output signal of the first address counter unit 33 and A, B, and the output is a load signal and a second. Selection signals S1 and S2 for driving the multiplexer section 32 are provided.

The clock generator 39, the flip-flop 40, and the first and second inverters 41 and 42, which are not described, are the same as in the conventional operation.

In addition, the selection signals S1 and S2 for driving the first multiplexer section 45 use the output of the second comparator section 48.

The input of the second comparator unit 48 is composed of the output value of the second address counter unit 34, the output of the first multiplexer unit 45, and the inputs of the second address counter unit 34. An output of the first multiplexer section 45 is made.

The output of the second address counter section 34 enters the address input of the second line memory section 36.

In addition, the output of the flip-flop 40 controls the enable terminals of the first and second comparators 38 and 48.

FIG. 5 shows a process of descrambling by rewriting after rewriting, and FIG. 5 (a) shows a scrambled video signal and (b) shows right writing where the first to fourth sections are written as they are. , (c) indicates data and address relations of the first and second line memory sections 35 and 36, and (d) indicates rewriting and includes one section, three sections, two sections, and four sections. , (e) indicates the descrambling video signal.

First, the process of descrambling the rewrite after straight writing of FIG. 5 will be described. When the digital video signal is stored in the first and second line memory units 35 and 36, the fifth and second lines of FIG. Similarly, when reading (writing) and reading, the two sections and the three sections are interchanged and read as shown in (d) of FIG.

At this time, unlike in Figure 2 it can be seen that the boundary point between the second section and the third section is (A + B-P), not P.

Therefore, when rewriting after right writing, (A + B-P) value should be input to the first multiplexer part 45 of FIG. 4 instead of P value.

However, this is because the second multiplexer unit 32 in FIG. 5 reads immediately after rewriting as in the prior art, and the second line memory unit 36 reversely reads after rewriting.

Therefore, in the load signal of the first address counter 33, a signal such as (d) of FIG. 6, which is the signal waveform of each part of FIG. 4, is generated in the first comparator 38 and the second address is conventionally used. The load signal of the counter section 34 is generated by the second comparator section 48 as shown in FIG.

At this time, since the first line memory unit 35 is in the write mode, it is rewriting, and the second line memory unit 36 is in the read mode, so it is rewritten.

In the next horizontal scan line in FIG. 6, since the first line memory unit 35 reads directly and the second line memory unit 36 reads directly, data is input to the first and second address counter units 33 and 34. FIG. It does not need to be counted, but counts from 0 in order.

For this reason, the load signal is also kept high for the entire horizontal section.

This is because a signal as shown in FIG. 6 (b) is inputted to the first and second comparator parts 38 and 48, and the first and second comparator parts 38 and 48 cannot be disabled. The load signal is not generated.

In this way, during one horizontal section, as shown in (d) and (e) of FIG. 6, a load signal is generated at the same time so that the two signals can be easily synchronized using the A and B signals, which are common parts of (d) and (e) of FIG. The load signal is not generated in both horizontal sections.

As described in detail above, the present invention generates load signals, which are the most important part of the address counter, separately, so that each load signal is easily synchronized to the horizontal synchronization, and the image quality deterioration can be prevented when descrambling. There is.

Claims (2)

P (pulse) value obtained by the random noise generating means, (A + BP) value obtained by subtracting the address (A + B) added by the adder through the subtractor and the P value are provided to the first and second multiplexers, respectively. And rewriting the first and second multiplexer sections as data of the first and second address counter sections, and using the outputs of the first address counter section as the address input of the first line memory section. And rewriting the output after the second address counter unit as the address input of the second line memory unit, and immediately rewriting the first address counter unit, and outputting the first address counter unit as the input of the first comparator unit therefrom. Obtaining a load signal, using the output of the second address counter unit as an input of the second comparator unit, and obtaining a load signal from the second address counter unit therefrom; A horizontal synchronous signal passed through an inverter and a flip-flop is an enable signal of the first and second comparator units, or a read / write signal of the second line memory unit or a read / write signal of the first line memory unit via the first inverter. The image read / write conversion method of the scrambling system, characterized in that the step is made to use. A random noise generator which removes noise from the input horizontal synchronization signal to generate a P value, an adder which adds and outputs an input address (A) (B), and an A + B value and random noise generator which are added from the adder A subtractor for outputting an A + BP value by subtracting the P value generated from the external signal; and an external selection signal S1 for one of an A + BP value output from the subtractor and an A, B, 0 value input from the outside. A first multiplexer section selected and output by S2 and one of a P value generated by the random noise generator and an A, B, 0 value input from the outside to an external selection signal S1 (S2); A first address counter unit for counting the output selected by the second multiplexer unit by a second multiplexer unit selected by the second multiplexer unit, a clock signal of the clock generation unit receiving the horizontal synchronization signal, and an external load signal; Generator clock A second address counter unit for counting an output selected by the first multiplexer unit as a data by a call and an external load signal, and inverting the horizontal synchronizing signal through a second inverter and performing chip in accordance with the inverted horizontal synchronizing signal. The output signal of the flip-flop generating the enable signal is compared with the P value of the random noise generating unit, the output value of the second address counter unit, and the input A and B values. A first comparator unit for outputting a load signal to the first address counter unit, a P value of the random noise generator unit, an output value of the second address counter unit, and an input A according to the chip enable signal of the flip-flop; A second comparator which compares the B value and accordingly outputs the selection signals S1 and S2 to the first multiplexer section and outputs a load signal to the second address counter section; And a first inverter for inverting the output signal of the flip-flop and outputting it as a read / write signal, and a counter at the first and second address counters according to the read / write signal of the first inverter and the clock signal of the clock generator. An image reading / writing converting apparatus of a scrambling system, characterized by comprising first and second line memory sections for reading / writing one data.

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