KR910007727B1 - 인터럽트 처리방법 및 장치 - Google Patents

인터럽트 처리방법 및 장치 Download PDF

Info

Publication number
KR910007727B1
KR910007727B1 KR1019880016806A KR880016806A KR910007727B1 KR 910007727 B1 KR910007727 B1 KR 910007727B1 KR 1019880016806 A KR1019880016806 A KR 1019880016806A KR 880016806 A KR880016806 A KR 880016806A KR 910007727 B1 KR910007727 B1 KR 910007727B1
Authority
KR
South Korea
Prior art keywords
signal
cpu
interrupt
irr
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019880016806A
Other languages
English (en)
Korean (ko)
Other versions
KR890010730A (ko
Inventor
신지 니시까와
히로유끼 후지야마
고우이찌 구로이와
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
후지쓰 마이크로컴퓨터 시스템스 가부시끼가이샤
시무라 도시유끼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마, 후지쓰 마이크로컴퓨터 시스템스 가부시끼가이샤, 시무라 도시유끼 filed Critical 후지쓰 가부시끼가이샤
Publication of KR890010730A publication Critical patent/KR890010730A/ko
Application granted granted Critical
Publication of KR910007727B1 publication Critical patent/KR910007727B1/ko
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
KR1019880016806A 1987-12-18 1988-12-16 인터럽트 처리방법 및 장치 Expired KR910007727B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-321905 1987-12-18
JP62321905A JPH01162967A (ja) 1987-12-18 1987-12-18 割込み処理方法及び装置
JP?62-321905 1987-12-18

Publications (2)

Publication Number Publication Date
KR890010730A KR890010730A (ko) 1989-08-10
KR910007727B1 true KR910007727B1 (ko) 1991-09-30

Family

ID=18137712

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880016806A Expired KR910007727B1 (ko) 1987-12-18 1988-12-16 인터럽트 처리방법 및 장치

Country Status (4)

Country Link
US (1) US5119496A (enExample)
EP (1) EP0321240B1 (enExample)
JP (1) JPH01162967A (enExample)
KR (1) KR910007727B1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237692A (en) * 1990-11-09 1993-08-17 Ast Research Inc. Internal interrupt controller for a peripheral controller
JP2928066B2 (ja) * 1993-11-05 1999-07-28 群馬日本電気株式会社 バス線長認識装置
JP3242508B2 (ja) * 1993-11-05 2001-12-25 松下電器産業株式会社 マイクロコンピュータ
US5671421A (en) * 1994-12-07 1997-09-23 Intel Corporation Serial interrupt bus protocol
DE19504488C1 (de) * 1995-02-10 1996-06-20 Siemens Ag Verfahren zur Initialisierung von peripheren Einrichtungen durch eine programmgesteuerte Zentraleinrichttung eines Kommunikationssystems
US5812796A (en) * 1995-08-18 1998-09-22 General Magic, Inc. Support structures for an intelligent low power serial bus
US6076124A (en) * 1995-10-10 2000-06-13 The Foxboro Company Distributed control system including a compact easily-extensible and serviceable field controller
KR100393765B1 (ko) * 1996-03-26 2004-03-10 엘지전자 주식회사 인터럽트제어장치
JPH1027150A (ja) * 1996-07-09 1998-01-27 Murata Mach Ltd 情報処理装置及び外部装置
US5848279A (en) * 1996-12-27 1998-12-08 Intel Corporation Mechanism for delivering interrupt messages
US5964815A (en) * 1997-10-21 1999-10-12 Trw Inc. Occupant restraint system having serially connected devices, a method for providing the restraint system and a method for using the restraint system
US6374320B1 (en) 1998-08-10 2002-04-16 Micron Technology, Inc Method for operating core logic unit with internal register for peripheral status
US6219720B1 (en) * 1998-08-10 2001-04-17 Micron Technology, Inc. Core logic unit with internal register for peripheral status
US6189049B1 (en) 1998-08-10 2001-02-13 Micron Technology Method for operating processor with internal register for peripheral status
US6233627B1 (en) 1998-08-10 2001-05-15 Micron Technology, Inc. Processor with internal register for peripheral status
DE19906867C1 (de) * 1999-02-18 2000-07-06 Weidmueller Interface Verfahren und Vorrichtung zur seriellen Datenübertragung
US7814046B2 (en) * 2006-09-29 2010-10-12 Lam Research Corporation Dynamic component-tracking system and methods therefor
US8775516B2 (en) * 2010-03-26 2014-07-08 Seiko Epson Corporation Projector system and connection establishment method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766530A (en) * 1972-07-21 1973-10-16 Rca Corp Communications between central unit and peripheral units
US4209838A (en) * 1976-12-20 1980-06-24 Sperry Rand Corporation Asynchronous bidirectional interface with priority bus monitoring among contending controllers and echo from a terminator
US4225942A (en) * 1978-12-26 1980-09-30 Honeywell Information Systems Inc. Daisy chaining of device interrupts in a cathode ray tube device
JPS5857770B2 (ja) * 1979-06-22 1983-12-21 パナファコム株式会社 情報転送制御方式
US4380052A (en) * 1980-09-15 1983-04-12 Burroughs Corporation Single transmission bus data network employing a daisy-chained bus data assignment control line which can bypass non-operating stations
US4641266A (en) * 1983-11-28 1987-02-03 At&T Bell Laboratories Access-arbitration scheme
US4617566A (en) * 1983-12-15 1986-10-14 Teleplex Corporation Addressable-port, daisy chain telemetry system with self-test capability
GB8612396D0 (en) * 1986-05-21 1986-06-25 Hewlett Packard Ltd Chain-configured interface bus system

Also Published As

Publication number Publication date
EP0321240A3 (en) 1990-05-16
EP0321240A2 (en) 1989-06-21
US5119496A (en) 1992-06-02
JPH01162967A (ja) 1989-06-27
KR890010730A (ko) 1989-08-10
JPH0574111B2 (enExample) 1993-10-15
EP0321240B1 (en) 1994-07-27

Similar Documents

Publication Publication Date Title
KR910007727B1 (ko) 인터럽트 처리방법 및 장치
US4488231A (en) Communication multiplexer having dual microprocessors
US5454085A (en) Method and apparatus for an enhanced computer system interface
US4385382A (en) Communication multiplexer having a variable priority scheme using a read only memory
EP0458304A1 (en) Direct memory access transfer controller
EP0147599B1 (en) Data processing system including a main processor and a co-processor and co-processor error handling logic
US4703418A (en) Method and apparatus for performing variable length data read transactions
JPH01237864A (ja) Ｄｍａ転送制御装置
US4779190A (en) Communication bus interface
US4523277A (en) Priority interrupt system for microcomputer
US4482982A (en) Communication multiplexer sharing a free running timer among multiple communication lines
US4380065A (en) Communication multiplexer variable priority scheme
AU613115B2 (en) Secure commodity bus
EP0331487B1 (en) Data transfer control system
US5640570A (en) Information handling system for transmitting contents of line register from asynchronous controller to shadow register in another asynchronous controller determined by shadow register address buffer
EP0049158B1 (en) I/o data processing system
JPS6215899B2 (enExample)
JPS623361A (ja) ステ−タス通報方式
JPS6242306B2 (enExample)
US4969090A (en) Program routine vectoring circuit for selectively using either stored interupt instructions or incoming interupt handling instructions
US4405981A (en) Communication multiplexer having an apparatus for establishing a single line priority
JP2558728B2 (ja) 異常割込み処理装置
EP0171940A1 (en) A direct memory access device and a method of using the device in a data transfer system
JPS61100854A (ja) 信号処理回路
JPH07175744A (ja) チャネル制御方式

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

FPAY Annual fee payment

Payment date: 20030924

Year of fee payment: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20041001

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20041001

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000