KR910005480Y1 - Bus distribution circuit - Google Patents

Abstract

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Description

Bus distribution circuit

1 is a conventional circuit diagram.

2 is a circuit diagram according to the present invention.

3 is a detailed circuit diagram of a bus arbiter 40 according to the present invention.

4 is a waveform diagram of each part according to the present invention.

* Explanation of symbols for main parts of the drawings

10, 20: 1st, 2nd CPU 30: common memory

40: bus arbiter G11, G12: delay part

G13, G14: Oagate G15-G18: Three-phase buffer

G19, G20: Bidirectional buffer

The present invention relates to a multi-processor system, and more particularly, to a circuit for equally distributing a bus use right to central processing units (CPUs) on both sides.

In general, when multiple CPUs simultaneously request a bus license, the bus license is granted only to the CPU with the highest priority. Fig. 1 shows a conventional circuit diagram in which bus use rights are allowed in the above manner. In FIG. 1, the first and second n When two CPUs simultaneously request memory usage rights, priority encoders (1) and decoders (2) allow fixed priority to a specific CPU. . Therefore, as the number of simultaneous requests increases, the memory usage distribution between the two CPUs becomes uneven, resulting in a decrease in system performance.

Therefore, the purpose of the present invention is that if the CPU that called the license first among the two CPUs can use the common memory, and simultaneously calls the license, the priority is lowered to the CPU that acquired the license before the simultaneous call among the two CPUs, so that one CPU is continuously memoryd. It is to provide a bus distribution circuit that makes it impossible to obtain a license.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a circuit diagram according to the present invention, in which the first and second CPUs 10 and 20, the common memory 30, and the first and second CPUs 10 and 20 simultaneously display the first and second request signals. When the common memory 30 is requested to be used, the bus arbiter 40 is configured to lower the priority of the CPU that has obtained the right of use before the simultaneous call so that only one CPU is allowed to call.

3 is a detailed circuit diagram of the bus arbiter 40 according to the present invention.

4 is an angle waveform diagram according to the present invention.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. 2-4.

The first and second request signals And The first and second response signals to the REQ1 and REQ2 signals are referred to as signals. Signal, and the first and second read / write control signals It is called a control signal. When the first and second CPUs 10 and 20 have one common memory 30, each of the first and second CPUs 10 and 20 is used to use the common memory 30 by a decoder. Signal and Generate a signal. Generated from the first and second CPUs 10 and 20 Signal and The signal is input to the input terminals P1 and P2 of the bus arbiter 40 to lower the priority to the CPU that has obtained the right to use the simultaneous call, so that only one CPU is allowed to call. Thus, the call permission signal according to the CPU call is output to only one of the terminals allowing the call through the output terminals P4 and P7 of the bus arbiter 40. The call permission signal is applied to the tri-state buffers G17 and G18 and the control terminals and according to the control signals of the three-state buffers G17 and G18. Control signal and The control signal is transferred to the common memory 30 through the tri-state buffers G17 and G18. Connect with the terminal.

remind , According to the control signal, the data buses Data Bus 1 and Data Bus 2 of the first and second CPUs 10 and 20 on the CPU side are controlled by controlling the direction terminals Dir of the bidirectional buffers G 19 and G 20. ) Is connected to the data terminal (D0-Dm). In addition, by controlling the control terminals of the three-state buffer (G15, G16) in accordance with the operation state of the bidirectional buffer (G19, G20), the address bus (Address Bus1, Address Bus2) is connected to the address terminals A0-An of the common memory 30. Since the bus on the CPU side of the call allowed is connected to the common memory 30, a call allowance signal output from the bus arbiter 40 is used for a time for using the common memory 30 through the delay units G11 and G12. To secure.

After securing the output signal of the delay unit (G11, G12) is input to the first input terminal of the oragate (G13, G14) And The signal is input to the second input terminal, and the two input signals are logically operated on to the first and second CPUs 10 and 20 to send a response to the CPU side which is allowed to call. Output the signal.

The CPU that is allowed to call among the first and second CPUs 10 and 20 Receive the signal and end the bus cycle Release the signal. The bus arbiter 40 disconnects the CPU bus connected to the common memory 30 so that the counterpart CPU may use the common memory 30. The operation of the bus arbiter 40 will be described with reference to FIG. 3.

P1 and P2 of the bus arbiter 40 input a request signal for each CPU to use a common memory, and P4 and P7 are license permission response outputs according to CPU calls. P8 like the signal of FIG. 4f connected to the common selection terminal CS of the common memory 30 generates an output signal indicating that one of the first and second CPUs 10 and 20 has obtained the right to use. P3, like the signal in FIG. 4E, indicates that a status signal is stored which remembers which CPU was previously licensed and indicates that the second CPU 20 on the input terminal P2 side has called when P3 = 0. . The oragates G1 and G5 are judgments for granting a use right when the first and second CPUs 10 and 20 on both sides of P1 and P2 make a call request. Also, the oA gates G2 and G4 make a judgment for granting a use right when only a CPU of either P1 or P2 is called. The first CPU 10 can use the common memory 30 to the P1 side. When this signal is input, P1 = 0 and P2 = 1, as shown in the signals (a) and (b) of section (a) of FIG. 4. The signals on the P1 and P2 sides are input to the oragates G1, G2, G4, and G5, the signals on the P3 side are input to the oragate G1, and the signals inverted to the oragate G5 are input. In addition, a signal in which the signal on the P5 side is inverted to the oragate G4 is input and a signal in which the signal on the P6 side is inverted to the oragate G2 is input. The output signals of the ORGAART G1 and G2 are input to the AND gate G3, and the output signals of the ORGATE G4 and G5 are input to the AND gate G6. The AND gates G3 and G6 output are inputted to the AND gate G7 to be connected to P8. Thus, P4 connected to the output terminal of the AND gate G3 by the oragate G2 and the AND gate G3 becomes 0 as shown in the 4c diagram, so that the first CPU 10 on the P1 side uses the common memory 30. Done. Since the signals of P4 and P7 are inputted to the AND gate G7 and 0 is output to P8, the signals of P8 are inputted to the clock terminal CK of the JK flip-flop G10.

In addition, the power supply (+ 5V) is supplied to the input terminals J and K of the J-K flip-flop G10, and the signal of the P4 side is input to the clear terminal C to clear the J-K flip-flop G10. Clearing the above, 0 is output to the output terminal Q and the P1 side has a high priority so that the right of use cannot be transferred to the input terminal P2 side when the P2 side calls during the P1 side call. When the signal on the P4 side is input to the first CPU 10, the first CPU 10 releases the license request after the minimum time required for the CPU to read and write data in consideration of the memory access time has elapsed. This takes 1 on the P1 side. At this time, at the same time when the license request is released (P1 = 1, P2 = 1), the J-K flip-flop G10 is inverted and toggled so that the priority of the input terminal P2 is high. The terminal P5 is extended by the delay through the delay unit G8 by P4 = 0 by the delay time td of FIG. 3b, so that the right of use on the input terminal P2 is the oragate G4 during the delay time td. Do not type in.

4 (b) is a section on the P2 side where the second CPU 20 can use the common memory 30. When a signal is inputted, P1 = 1 and P2 = 0, as in the signals (a) and (b) of FIG. 3 (b). P1 = 1, P2 = 7, and the outputs of the AND gates G3, G6 are 1,0, respectively, and P4 = 1, P7 = 0. P7 = 0 is input to the set terminal S of the JK flip-flop G10, and high is output to the output terminal Q, so that P3 becomes 1. P7 = 0 is applied to P6 through the delay unit G9 and to the oragate G2. When only one of P1 and P2 is requested, call permission signals are output to P4 and P7 regardless of the state of P3 by OA gates G2 and G4. Therefore, according to the operation of the JK flip-flop (G10) clear terminal (C) and the set terminal (5), the side that has obtained the calling right has a high priority so that the right is maintained without being reversed when the other side requests. When both the P1 and P2 make a call request at the same time, the call permission is determined by the OA gates G1 and G5 and the JK flip-flop G10 as shown in section (c) of FIG.

Since the second CPU 20 on the P2 side obtained the call right during the fourth section (b), the terminal P3 = 0 after the section (b), and the first CPU on the P1 side by the OA gates G1 and G5. (10) is allowed to call. Thus, P4 and P7 are P4 = 0 and P7 = 1, which are (c) and (d) in the fourth section (c), and the second CPU 20 on the P2 side is in a standby state. After the P4 = 0 inputs to the first CPU 10 and the first CPU 10 releases a short time later, the first CPU 10 is released (P1 = 1, P2 = 1) by the delay unit G8. If it is delayed by (td) and input to the OR gate G4, it becomes the call permission of the 2nd CPU 20 of P2 side. In the section 4 (d) of FIG. 4, the P2 side last obtained the call right in the (c) section, but P3 = 0, that is, the priority of the P1 side is high, but since the call of the P1 side is not available, the call is allowed by the request of the P2 side. Becomes

As described above, when the common memory is used by multiple CPUs, the higher the number of simultaneous calls of each CPU, the priority is changed so that the CPU side which is already allowed to call has lower priority compared to the priority encoder and decoder bus divider. Therefore, there is an advantage of increasing the overall system performance by having equal calling opportunities on both CPUs.

Claims (2)

In a multiprocessor system having first and second CPUs 10 and 20 and a common memory 30, the first and second CPUs 10 and 20 simultaneously use the common memory 30 when the first and second request signals are generated. A bus distribution circuit comprising: a bus arbiter 40 configured to lower the priority of a CPU that has been licensed prior to a simultaneous call, and to permit a call to any one CPU when a request is made. 2. The apparatus according to claim 1, wherein the bus arbiter 40 makes a judgment for granting a use right when both CPUs call simultaneously or when only one CPU requests a call, and the judgment of the first means. The second means for transferring the priority after the end of the call while maintaining the priority of the calling CPU according to the call permission, and the third means for delaying a predetermined delay to secure the interval before the call right of the second means. Bus distribution circuit, characterized in that.