JPH0216667A - Processor system - Google Patents

Abstract

PURPOSE:To eliminate the waiting state of a CPU card for an interruption cycle when an interruption is made form an I/O card by causing the CPU card to issue a bus right request which is higher in level than ordinary requests and acquiring the bus right. CONSTITUTION:The bus right requesting level of a bus right request circuit 14 is set higher than that of another bus right request circuit 13. When a CPU card 1 acquires the bus right of a system bus SB during ordinary operations, the card 1 selects the circuit 13 through a switching section 15 and acquires the system bus right. On the other hand, when a bus right request is made from an I/O card and an interruption is made to the CPU card 1, a CPU 11 selects the circuit 14 through the switching section 15 and makes a high-level bus right request to obtain the bus right of the system bus SB and an interruption handler 12 starts an interruption approving cycle with the I/O card making the interruption. Since the card 1 makes the bus right request which is higher in level than ordinary requests, the card 1 can certainly acquire the bus right of the bus SB and the interruption approving cycle to the I/O card can be executed with no waiting time.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a processor/processor that executes various processes by connecting a CPU card and a plurality of I/O cards that issue bus rights requests via a system bus. Regarding the system, this invention relates to improving the interrupt response time of the CPtJ card when a bus request is issued to the I/O card.

<Prior Art> In a processor system in which a CPtJ card and multiple I/O cards are connected to a system bus, each I/O card
The O card acquires the bus right and performs DMA transfer or notification of processing completion by interrupt. In addition to reading programs, reading and writing data, the CPU card acts as an interrupt handler and accepts interrupts from the I/O card, and executes an interrupt acknowledgment cycle to identify the source of the interrupt.

Two or more bus arbitration levels are set in the bus arbiter in such a processor system, and only one bus arbitration level is set for each I/O card.

Normally, the bus right request level of an I/O card is determined based on its urgency and the fact that it is on the downstream side of the daisy chain.
Set higher than the bus request level of the CP IJ card. Therefore, for the CPU card, the 1/O card is the system
The system is configured to use the system bus when the bus is not in use.

<Problem to be Solved by the Invention> When T/O cards are generating bus requests one after another, even if the CP tJ card attempts to start an interrupt acknowledgment cycle for one T/O card, When the next T/O card requests bus rights, the bus rights are taken away.
The CP tJ card may not be able to take bus ownership forever, resulting in a waiting state for interrupt processing.

As described above, conventional processor systems have a problem in that interrupt cycles require a certain degree of immediate responsiveness, but this condition cannot be satisfied.

An object of the present invention is to eliminate the waiting state of the interrupt cycle of the CP tJ card, and to improve the interrupt response time of the entire system.

Means for Solving the Problems> In order to solve the above problems, the present invention sets two bus right request levels in the CPU card, and its configuration is as follows.

That is, the present invention provides a processor system that connects a CPU card and a plurality of T/O cards that issue bus rights requests via a system bus, wherein the CP LJ card is connected to a normal system bus. The processor system is characterized in that a bus right request level is set higher than an access level, and the bus right is requested at the higher level in an interrupt acknowledgment cycle.

Effect> In the processor system of the present invention, when an interrupt occurs from the T/O card, the CP LJ card issues a bus request at a higher level than a normal bus request to acquire the bus right, Initiate an interrupt acknowledgment cycle with the T/O card requesting the interrupt.

<Example> The figure shows a CP in a processor system implementing the present invention.
This is a diagram showing the configuration of the LJ card, and shows the system bus S.
CPU card 1 is connected to B.

Although not shown in the diagram, the system bus SB usually has
Multiple T/O cards are connected.

The CPU card 1 includes a CPU 1l that controls this card;
An interrupt handler 12 that accepts interrupts from the T/O card, a first bus request circuit 13 that generates a bus request in order for this CPtJ card 1 to perform normal bus access, and a T/O card. The second bus request time f%14 acquires the bus right in order to accept the interrupt and start the interrupt acknowledgment cycle, and the switching unit 15 switches between the first or second bus request circuit 13 or have

The bus request level of the second bus request circuit 14 is set higher than the bus request level of the first bus request circuit 13. Also, the first bus request time 1m13 is the bus request time 1m13.
The second bus right request circuit 14 outputs the request BR-1ov+ and forms a daisy chain with other cards using the bus ground RG I-low and BGO-OW, and the second bus request circuit 14 outputs the bus request BR-h+gh. Bus Grand BG I-high,
B G 0-hiQh forms a daisy chain with other cards.

Now, the operation of the processor system of the present invention in which the CPU card is configured in this manner will be described below.

On system bus SB, a bus request signal (bus
When a request BR) is asserted, a bus arbiter (not shown) asserts a bus ground (BG) in response to the bus request BR having the highest request level.

Bus ground (BG) is transmitted by a daisy chain, and a card outputting a bus request BR at this level acquires the bus right of the system bus, and a card not requesting the bus right or a card other than this level The card generating the bus request at the level of BG transmits this bus ground (BG) to the next card.

When the CPU card 1 acquires the system bus right in normal operation (program reading, data writing, etc.), the first bus request circuit 13 is selected by the switching unit 15 in order to generate a low-level bus request. Then, it acquires the system bus right by bus request BR-/OW and bus ground BGI-low.

When a bus request is generated from another I/O card and an interrupt is made to the CPU card 1, the CPU II selects the second bus request time N14 by the switching unit 15 and makes a high-level bus request BR. -high, bus ground B
The interrupt handler 12 acquires bus ownership of the system bus SB by G I-high, and starts an interrupt acknowledgment cycle with the I/O card that issued the interrupt.

At this time, since the CPtJ card 1 is issuing a bus request at a higher level than usual, it can reliably acquire the bus right to the system bus SF and allocate the I/O card without any waiting time. can run an approval cycle.

<Effects of the Invention> As described above, the processor system of the present invention has the following effects:
It is possible to eliminate the waiting state of the interrupt cycle of the CPU card, and it is possible to improve the interrupt response time of the entire system.

[Brief explanation of the drawing]

The figure shows CP LJ in the processor system of the present invention.
FIG. 3 is a diagram showing the configuration of a card. 1...CP tJ card, 11...CP tJ, 1
2... Interrupt handler, 13... First bus request circuit, 14... Second bus request circuit, SB... System bus.

Claims (1)

[Claims] (1) A processor system that connects a CPU card and a plurality of I/O cards that issue bus rights requests via a system bus, wherein the CPU card is accessed at a level higher than that of normal system bus access. 1. A processor system, wherein a high bus right request level is set, and an interrupt acknowledgment cycle requests a bus right at the high level.