KR950001232B1 - Circuit for arbitrating bus in map network adaptor - Google Patents

Abstract

The bus arbitration circuit enables a processor and a token-bus controller to access the shared memory region without polling and interrupt in order to remove data-conflict. The MAP network controller comprises a processor, a token-bus controller, a shared memory region, a bus arbitration circuit. The bus arbitration circiut comprises the first D flip-flop inputting bus request from the token-bus controller and outputting bus hold signal; the second D flip-flop inputting bus hold acknowledge signal and outputting bus grant to the token-bus controller; AND gate arbitrating the bus access right.

Description

Bus arbitration circuit in MAP network connector

1 is a schematic block diagram of the present invention.

2 is a detailed circuit diagram of the present invention.

3A to 3E are signal waveform diagrams for explanation in the present invention.

* Explanation of symbols for main parts of the drawings

10: processor 20: token bus controller

30: bus arbitration circuit 40: shared memory area

FF ₁ , FF ₂ : D flip-flop AND: AND gate

: Bus Request Signal

: Bus Grant

HOLD: Bus stop signal

HLDA: HOLD Acknowledge

: Bus Grant Acknowledgment

PCS: Peripheral Chip Selection Circuit

CS: Chip Select Circuit : System reset signal

The present invention relates to a bus arbitration circuit in a MAP network connector for eliminating data collision using a bus arbitration circuit.

Conventionally, a polling method or an interrupt method is mainly used to access a memory area shared by an 80186 processor and a token bus controller.

The polling method uses a register or a part of memory as a flag, and when a 80186 processor or token bus controller wants to use its bus, it checks a specific bit of the flag at regular intervals, and the bit is set to '1'. If it is set to '0', it waits until it becomes '0' and if it becomes '0', it sets '1' to the bit checked by the other party and then uses its own bus.

However, this method requires a register or memory to be added to the circuit to prevent data collisions on the bus, and the circuit configuration is complicated. Therefore, the 80186 processor or the token bus controller always checks the state of the flag at regular intervals. Has a bad disadvantage.

The interrupt method generates an interrupt when the user wants to use the bus and requests a bus license. In this case, a separate complicated circuit such as an interrupt arbiter and an interrupt handler is required. Since it is possible to stop the operation of the other party unilaterally, it is not suitable for a system in which data is always transmitted and received from the outside, such as in a MAP network connector.

Accordingly, the present invention provides a 80186 processor or token with a simple bus arbitration device composed of two flip-flops and one end gate without using a polling method or an interrupt method in order to avoid data collision during the 80186 processor and token bus control period. This allows the bus controller to access the shared memory area in a timely manner without using flag checks and interrupts at regular intervals so that there is no data collision on the bus.

Therefore, the present invention has a much simpler circuit configuration than the conventional polling or interrupting method, and has much superior advantages in terms of efficient system.

Now look at the configuration of the present invention to eliminate the data collision as follows. 1 is a block diagram of a bus arbitration circuit of a MAP network connector, in which an 80816 processor 10, a token bus controller 20, a shared memory area 40, and an 80816 processor 10 and a token bus controller 20 are provided. The bus arbitration circuit 30 is constituted so that access to the shared memory area 40 used for information exchange is not overlapped with each other and can be accessed at an appropriate time. The bus arbitration circuit 30 is composed of D flip-flops FF ₁ , FF ₂ and an AND gate AND, as shown in FIG. 2.

Referring to the operation and effect of the present invention configured as described above according to Figure 2 and 3 as follows.

2 is a detailed circuit diagram of the present invention, in which the token bus controller 20 sends a bus request signal to the 80816 processor 10 in order to obtain a bus. It starts from the point of outputting).

In this way, the token bus controller 20 uses the bus request signal as shown in FIG. ), The bus request signal ( ) Is input to the clear terminal CL of the D flip-flop FF ₁ , and at the same time to the 80186 processor 10 through the output terminal Q of the D flip-flop FF ₁ . The same bus stop signal HOLD is input.

When the bus stop signal HOLD is input to the 80816 processor 10, the 80186 processor 10 ends the current bus cycle and outputs the bus stop permission signal HLDA as shown in FIG. 3d. This signal is input to the clock terminal CLK of the D flip-flop FF ₂ , and at the same time through the output terminal Q of the D flip-flop FF ₂ , the bus permission signal as shown in FIG. ) Is entered. Since the bus permission signal BG means that the bus has acquired the bus to the token bus controller 20, the token bus controller 20 uses the same bus permission confirmation signal as in FIG. ) And use the system's bus itself.

Therefore, when the token bus controller 20 terminates the use of the bus, the bus grant confirmation signal BGACK is changed from the low state to the high state, wherein the high signal is transmitted through the AND gate. It is input to the clock terminal CLK of the D flip-flop FF1 to make the bus stop signal HOLD low, and the 80186 processor acquires the bus again.

As described above, the present invention provides a simple bus arbitration circuit composed of two flip-flops and one AND gate in order to eliminate data collision between the processor and the token bus controller. Access to shared memory areas can be accessed in a timely manner without state checking and the use of complex interrupts, thereby preventing data collisions on the bus.

Claims (1)

A shared memory area formed between the 80816 processor 10 and the token bus controller 20 that transmits and receives a predetermined control signal to perform its own bus right, and the 80186 processor 10 and the token bus controller 20. And a bus arbitration circuit 30 for arbitrating access to the bus 40 to prevent data collisions on the bus. The bus arbitration circuit 30 includes a bus request signal (i.e., a bus request signal). 1D flip-flop (FF1) for receiving a bus and outputting a bus stop signal (HOLD) for requesting the processor 10 to stop using the currently operating bus; The bus stop signal HLDA of the processor 10 is input to the bus bus signal 20 to the bus bus controller 20. ) 2D flip-flop FF2 for outputting; And an AND gate (AND) for arbitrating the bus usage authority in accordance with a predetermined control signal.