KR910003480A - 1비트/2비트 플레인 겸용 비디오 보드 - Google Patents

1비트/2비트 플레인 겸용 비디오 보드 Download PDF

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Publication number
KR910003480A
KR910003480A KR1019890010386A KR890010386A KR910003480A KR 910003480 A KR910003480 A KR 910003480A KR 1019890010386 A KR1019890010386 A KR 1019890010386A KR 890010386 A KR890010386 A KR 890010386A KR 910003480 A KR910003480 A KR 910003480A
Authority
KR
South Korea
Prior art keywords
bit
predetermined
video output
input terminal
shift register
Prior art date
Application number
KR1019890010386A
Other languages
English (en)
Other versions
KR920002600B1 (ko
Inventor
배시규
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019890010386A priority Critical patent/KR920002600B1/ko
Priority to GB9003424A priority patent/GB2234094B/en
Priority to DE4005993A priority patent/DE4005993A1/de
Priority to FR9002488A priority patent/FR2650090B1/fr
Priority to US07/488,724 priority patent/US5327530A/en
Publication of KR910003480A publication Critical patent/KR910003480A/ko
Application granted granted Critical
Publication of KR920002600B1 publication Critical patent/KR920002600B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G09G1/165—Details of a display terminal using a CRT, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G1/167—Details of the interface to the display terminal specific for a CRT
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음.

Description

1비트/2비트 플레인 겸용 비디오 보드
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 블럭도.
제2도는 제1도중 제어신호 발생부의 구체회로도,
제3도는 제1도중 메모리의 구체회로도.

Claims (2)

  1. 퍼스널 컴퓨터에 있어서, 상기 퍼스널 킴퓨터의 제어를 받아 비디오 보드 동작을 제어하는 그래픽 프로세서(20)와, 상기 그래픽 프로세서(20)의 제어를 받아 화면 정보를 기입 및 독출하는 메모리(80)와, 상기 메모리(80) 로 부터 독출된 화면 정보를 각각 반씩 상.하위비트로 분리 버퍼링하여 선택적으로 출력하는 스위칭부(90)와, 상기 스위치부(90) 출력을 소정 횟수 쉬프트하여 1비트 혹은 2비트 플레인 선택 상태에 따라 소정 분주클럭을 변경하여 1비트 혹은 2비트 비디오 출력을 선택적으로 발생하는 비디오 출력제어부(100)와, 모니터로 상기 비디오 출력을 전송하는 커낵터(110)로 구성됨을 특징으로 하는 1비트/2비트 플레임 겸용 비디오 보드회로.
  2. 제1항에 있어서, 비디오 출력 제어부(100)가 소정 제어를 받아 상기 스위치부(90) 출력을 쉬프트하는 쉬프트 레지스터(101)와, 소정 주파수를 2배로 나누어 상기 쉬프트 레지스터(101)의 제1입력단(φ1)으로 인가하는 제산기(102)와, 사용자의 선택에 따라 소정 분주클럭을 상기 쉬프트레지스터(101)의 제1입력단(50)으로 직접 공급하거나 상기 제산기(100)로 공급하는 점퍼(103)로 구성됨을 특징으로 하는 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890010386A 1989-07-21 1989-07-21 1비트/2비트 플레인 겸용 비디오 보드 KR920002600B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019890010386A KR920002600B1 (ko) 1989-07-21 1989-07-21 1비트/2비트 플레인 겸용 비디오 보드
GB9003424A GB2234094B (en) 1989-07-21 1990-02-15 Video boards
DE4005993A DE4005993A1 (de) 1989-07-21 1990-02-26 Videokarte zum unterstuetzen sowohl eines 1-bitebenenbetriebs als auch eines 2-bitebenenbetriebs
FR9002488A FR2650090B1 (fr) 1989-07-21 1990-02-28 Carte video assurant un fonctionnement en mode de niveau 1 bit et un fonctionnement en mode de niveau 2 bits
US07/488,724 US5327530A (en) 1989-07-21 1990-02-28 Video board for serving both 1-bit plane operation and 2-bit plane operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890010386A KR920002600B1 (ko) 1989-07-21 1989-07-21 1비트/2비트 플레인 겸용 비디오 보드

Publications (2)

Publication Number Publication Date
KR910003480A true KR910003480A (ko) 1991-02-27
KR920002600B1 KR920002600B1 (ko) 1992-03-30

Family

ID=19288304

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890010386A KR920002600B1 (ko) 1989-07-21 1989-07-21 1비트/2비트 플레인 겸용 비디오 보드

Country Status (5)

Country Link
US (1) US5327530A (ko)
KR (1) KR920002600B1 (ko)
DE (1) DE4005993A1 (ko)
FR (1) FR2650090B1 (ko)
GB (1) GB2234094B (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581788A (en) * 1992-12-14 1996-12-03 At&T Global Information Solutions Company System for testing the functionality of video cord and monitor by using program to enable user to view list of modes and select compatible mode
DE19917016A1 (de) * 1999-04-15 2000-10-19 Philips Corp Intellectual Pty Schaltungsanordnung zur Parallel/Seriell-Umsetzung
CN100374984C (zh) * 2005-03-01 2008-03-12 联想(北京)有限公司 一种切换显卡工作频率的方法及装置
JP6742816B2 (ja) * 2016-05-26 2020-08-19 キヤノン株式会社 電子機器、表示装置及び表示制御方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4595917A (en) * 1983-06-13 1986-06-17 Vectrix Corporation Data processing technique for computer color graphic system
GB2152711A (en) * 1984-01-12 1985-08-07 Sinclair Res Ltd A digital computer
US4851834A (en) * 1984-01-19 1989-07-25 Digital Equipment Corp. Multiport memory and source arrangement for pixel information
US4858107A (en) * 1985-03-11 1989-08-15 General Electric Company Computer device display system using conditionally asynchronous memory accessing by video display controller
IL83515A (en) * 1986-10-14 1991-03-10 Ibm Digital display system
US4823286A (en) * 1987-02-12 1989-04-18 International Business Machines Corporation Pixel data path for high performance raster displays with all-point-addressable frame buffers
JPS63292185A (ja) * 1987-05-25 1988-11-29 日本電気株式会社 デジタル入出力回路
US4771279A (en) * 1987-07-10 1988-09-13 Silicon Graphics, Inc. Dual clock shift register
US4910687A (en) * 1987-11-03 1990-03-20 International Business Machines Corporation Bit gating for efficient use of RAMs in variable plane displays
US4967378A (en) * 1988-09-13 1990-10-30 Microsoft Corporation Method and system for displaying a monochrome bitmap on a color display

Also Published As

Publication number Publication date
GB2234094A (en) 1991-01-23
DE4005993A1 (de) 1991-01-31
US5327530A (en) 1994-07-05
GB2234094B (en) 1993-08-25
GB9003424D0 (en) 1990-04-11
KR920002600B1 (ko) 1992-03-30
FR2650090B1 (fr) 1994-09-23
FR2650090A1 (fr) 1991-01-25

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